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    Low voltage difference operated EEPROM and operating method thereof
    1.
    发明授权
    Low voltage difference operated EEPROM and operating method thereof 有权

    公开(公告)号：US10242741B1

    公开(公告)日：2019-03-26

    申请号：US15708493

    申请日：2017-09-19

    Applicant: YIELD MICROELECTRONICS CORP.

    Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Chia-Hao Tai

    IPC: G11C16/04 ,  H01L27/11521 ,  G11C16/14 ,  H01L29/78 ,  G11C16/10 ,  H01L29/788

    Abstract: The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. An ion implantation is performed by masking partial regions to prevent the existence of the conventional lightly doped drain (LDD) structure. An undoped region is formed in the semiconductor substrate under the two sides of the first electric-conductive gate, to increase the intensity of electric field between the gate and the substrate or between the gate and the transistor, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM. The present invention applies to the EEPROM with a single gate transistor structure.

    Non-volatile memory with a single gate-source common terminal and operation method thereof
    2.
    发明授权
    Non-volatile memory with a single gate-source common terminal and operation method thereof 有权
    具有单个栅极源公共端子的非易失性存储器及其操作方法

    公开(公告)号：US09281312B2

    公开(公告)日：2016-03-08

    申请号：US14325549

    申请日：2014-07-08

    Applicant: YIELD MICROELECTRONICS CORP.

    Inventor： Hsin-Chang Lin ,  Ya-Ting Fan ,  Wen-Chien Huang

    IPC: H01L27/115 ,  H01L49/02 ,  H01L29/423 ,  H01L29/788 ,  G11C16/12 ,  G11C16/14

    CPC classification number: H01L27/11521 ,  G11C16/12 ,  G11C16/14 ,  H01L27/11558 ,  H01L28/40 ,  H01L29/42324 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/94

    Abstract: A non-volatile memory with a single gate-source common terminal and an operation method thereof are provided. The non-volatile memory includes a transistor and a capacitor structure both embedded in a semiconductor substrate. The transistor includes a first dielectric layer, a first electric-conduction gate and several first ion-doped regions. The capacitor structure includes a second dielectric layer, a second electric-conduction gate and a second ion-doped region. The memory may further include a third ion-doped region below the second dielectric layer. The first and second electric-conduction gates are electrically connected to form a single floating gate of the memory cell. The source and second ion-doped region are electrically connected to form a single gate-source common terminal.

    Abstract translation: 提供了具有单个栅极源公共端子的非易失性存储器及其操作方法。 非易失性存储器包括两个嵌入在半导体衬底中的晶体管和电容器结构。 晶体管包括第一电介质层，第一导电栅极和几个第一离子掺杂区域。 电容器结构包括第二电介质层，第二导电栅极和第二离子掺杂区域。 存储器还可以包括在第二介电层下面的第三离子掺杂区域。 第一和第二导电栅极电连接以形成存储单元的单个浮置栅极。 源极和第二离子掺杂区域电连接以形成单个栅极 - 源极公共端子。

    Method for operating low-cost EEPROM array
    3.
    发明授权
    Method for operating low-cost EEPROM array 有权
    操作低成本EEPROM阵列的方法

    公开(公告)号：US09240242B1

    公开(公告)日：2016-01-19

    申请号：US14565644

    申请日：2014-12-10

    Applicant: YIELD MICROELECTRONICS CORP.

    Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Ya-Ting Fan ,  Yang-Sen Yeh ,  Cheng-Ying Wu

    IPC: G11C16/10 ,  G11C16/14 ,  G11C16/04 ,  G11C16/16

    CPC classification number: G11C16/14 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/107 ,  G11C16/16 ,  G11C16/24

    Abstract: A method for operating a low-cost EEPROM array is disclosed. The EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line and a second word line. The common source lines include a first common source line. Each sub-memory array includes a first memory cell and a second memory cell, which are respectively connected with the first and second word lines. Each of the first and second memory cells is also connected with the first bit line group and the first common source line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method operates all the operation memory cells and uses special biases to program or erase memory cells massively in a single operation.

    Abstract translation: 公开了一种用于操作低成本EEPROM阵列的方法。 EEPROM阵列包括位线，字线，公共源极线和子存储器阵列。 位线分为位线组。 字线包括第一字线和第二字线。 公共源极线包括第一公共源极线。 每个子存储器阵列包括分别与第一和第二字线连接的第一存储单元和第二存储单元。 第一和第二存储单元中的每一个也与第一位线组和第一公共源极线连接。 第一和第二存储器单元是操作存储器单元，并且对称地布置在第一公共源极线的两侧。 该方法操作所有的操作存储器单元并且使用特殊的偏置来在单个操作中大量编程或擦除存储器单元。

    Method for operating small-area EEPROM array
    6.
    发明授权
    Method for operating small-area EEPROM array 有权
    操作小区域EEPROM阵列的方法

    公开(公告)号：US09318208B1

    公开(公告)日：2016-04-19

    申请号：US14572931

    申请日：2014-12-17

    Applicant: YIELD MICROELECTRONICS CORP.

    Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Ya-Ting Fan ,  Yang-Sen Yeh ,  Cheng-Ying Wu

    IPC: G11C16/14

    CPC classification number: G11C16/14 ,  G11C16/10 ,  G11C16/16 ,  G11C2216/16 ,  H01L27/115

    Abstract: A method for operating a small-area EEPROM array is disclosed. The small-area EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line. The common source lines include a first common source line. Each sub-memory array includes a first, second, third and fourth memory cells, which are connected with two bit line groups, a word line and a common source line. The first and second memory cells are symmetric. The third and fourth memory cells are symmetric. The group of the first and second memory cells and the group of the third and fourth memory cells are respectively positioned at two sides of the first common source line. The method operates all operation memory cells and uses special biases to program or erase memory cells massively in a single operation.

    Abstract translation: 公开了一种用于操作小区域EEPROM阵列的方法。 小面积EEPROM阵列包括位线，字线，公共源极线和子存储器阵列。 位线分为位线组。 字线包括第一个字线。 公共源极线包括第一公共源极线。 每个子存储器阵列包括与两个位线组，字线和公共源极线连接的第一，第二，第三和第四存储器单元。 第一和第二存储单元是对称的。 第三和第四存储单元是对称的。 第一和第二存储单元的组以及第三和第四存储单元的组分别位于第一公共源极线的两侧。 该方法操作所有操作存储单元，并且使用特殊的偏置来在单个操作中大量编程或擦除存储器单元。

    Method of fast erasing low-current EEPROM array
    7.
    发明授权
    Method of fast erasing low-current EEPROM array 有权

    公开(公告)号：US10685716B1

    公开(公告)日：2020-06-16

    申请号：US16381324

    申请日：2019-04-11

    Applicant: YIELD MICROELECTRONICS CORP.

    Inventor： Hsin-Chang Lin ,  Cheng-Yu Chung ,  Wen-Chien Huang

    IPC: G11C16/04 ,  G11C16/16 ,  H03K19/094 ,  G11C16/08 ,  H01L27/115 ,  G11C16/34 ,  G11C16/14

    Abstract: A method of fast erasing a low-current EEPROM array. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The source or the drain is floated during erasing to perform the fast bytes-erasing with low current, low voltage and low cost.

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