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公开(公告)号：US20060187508A1
公开(公告)日：2006-08-24
申请号：US11347394
申请日：2006-02-06
IPC分类号： H04N1/46
摘要： The movement of an image component is determined using the plot information, such as the position, size of the image component, etc., at each time. The complex movement of each image component can be easily generated by providing a plurality of plot information generating units for each image component and combining a plurality of pieces of plot information generated by the plot information generating units when an image is reproduced.
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公开(公告)号：US07542165B2
公开(公告)日：2009-06-02
申请号：US11347394
申请日：2006-02-06
摘要： The movement of an image component is determined using the plot information, such as the position, size of the image component, etc., at each time. The complex movement of each image component can be easily generated by providing a plurality of plot information generating units for each image component and combining a plurality of pieces of plot information generated by the plot information generating units when an image is reproduced.
摘要翻译： 使用图形信息来确定图像分量的移动，例如每次的位置，图像分量的尺寸等。 通过为每个图像分量提供多个绘图信息生成单元，并且当图像被再现时组合由绘图信息生成单元生成的多个绘图信息，可以容易地生成每个图像分量的复杂运动。
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公开(公告)号：US07031018B1
公开(公告)日：2006-04-18
申请号：US09675049
申请日：2000-09-29
IPC分类号： G06F15/00
摘要： The movement of an image component is determined using the plot information, such as the position, size of the image component, etc., at each time. The complex movement of each image component can be easily generated by providing a plurality of plot information generating units for each image component and combining a plurality of pieces of plot information generated by the plot information generating units when an image is reproduced.
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公开(公告)号：US20080068623A1
公开(公告)日：2008-03-20
申请号：US11980666
申请日：2007-10-31
IPC分类号： G06F15/00
摘要： The movement of an image component is determined using the plot information, such as the position, size of the image component, etc., at each time. The complex movement of each image component can be easily generated by providing a plurality of plot information generating units for each image component and combining a plurality of pieces of plot information generated by the plot information generating units when an image is reproduced.
摘要翻译： 使用图形信息来确定图像分量的移动，例如每次的位置，图像分量的尺寸等。 通过为每个图像分量提供多个绘图信息生成单元，并且当图像被再现时组合由绘图信息生成单元生成的多个绘图信息，可以容易地生成每个图像分量的复杂运动。
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公开(公告)号：US08478654B2
公开(公告)日：2013-07-02
申请号：US13360478
申请日：2012-01-27
申请人： Yuuichirou Ikeda
发明人： Yuuichirou Ikeda
IPC分类号： G06Q30/00
CPC分类号： G06Q30/02
摘要： A device executes a program including a process stored in a storage device. The process includes obtaining possessed product information of a possessed product of a user, and usage status information which indicates usage of the possessed product, the process product information being based on a request from the user device, obtaining first product information corresponding to the obtained possessed product information and a second product information of a comparison target product, the first product information and the second product information including a content of the possessed product and the comparison target described in a plurality of items, respectively, extracting a prescribed item from among the items of the first product information and second product information based on the obtained usage status information, and transmitting the content based on the content of the first product information and second product information corresponding to the extracted item to the user device.
摘要翻译： 设备执行包括存储在存储设备中的过程的程序。 该处理包括获取用户的拥有产品的所拥有的产品信息，以及指示所拥有产品的使用的使用状态信息，所述处理产品信息是基于来自用户设备的请求，获得与获得的所拥有的对应的第一产品信息 产品信息和比较目标产品的第二产品信息，第一产品信息和第二产品信息，分别包括在多个项目中描述的所拥有产品和比较对象的内容，从项目中提取规定的项目 基于获得的使用状况信息获取第一产品信息和第二产品信息，并且基于与提取的项目相对应的第一产品信息和第二产品信息的内容向用户设备发送内容。
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公开(公告)号：US07164593B2
公开(公告)日：2007-01-16
申请号：US10850116
申请日：2004-05-21
申请人： Yuuichirou Ikeda
发明人： Yuuichirou Ikeda
IPC分类号： G11C5/06
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11
摘要： A storage section, at least one writing section, and at least one reading section are provided on a substrate. A storage-section substrate region in which the storage section is formed, at least one writing-section substrate region in which each writing section is formed, at least one reading-section substrate region in which each reading section is formed are insulatedly isolated from each other on the substrate. Independent substrate potentials are applied to each substrate region.
摘要翻译： 存储部分，至少一个写入部分和至少一个读取部分设置在基板上。 在其中形成有存储部的存储部基板区域，形成有各个写入部的至少一个写入部基板区域，形成有各读取部的至少一个读取部基板区域与每个读取部基板区域绝缘地隔离 其他在基材上。 将独立的衬底电位施加到每个衬底区域。
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公开(公告)号：US08441837B2
公开(公告)日：2013-05-14
申请号：US13054312
申请日：2010-04-14
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/12 , G11C2213/15 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.
摘要翻译： 一种非易失性电阻可变存储器件（100）包括存储单元（M11，M12 ...），每个存储单元包括可变电阻元件（R11，R12 ...），该可变电阻元件（R11，R12 ...） 第一电极和第二电极，以及包括放置在第三电极和第四电极之间并与第三电极和第四电极接触的电流导向层的电流导向元件（D11，D12 ...）串联连接，并且驱动该装置 通过第一LR驱动电路（105a1）经由限流电路（105b），以在器件被第二HR驱动电路（105a2）驱动时降低可变电阻元件的电阻，以增加可变电阻元件的电阻，从而使用 电流限制电路（105b），用于使可变电阻元件的电阻降低的电流低于用于增加可变电阻元件的电阻的电流。
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公开(公告)号：US20110122680A1
公开(公告)日：2011-05-26
申请号：US13054312
申请日：2010-04-14
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/12 , G11C2213/15 , G11C2213/34 , G11C2213/72 , H01L27/24
摘要： A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.
摘要翻译： 一种非易失性电阻可变存储器件（100）包括存储单元（M11，M12 ...），每个存储单元包括可变电阻元件（R11，R12 ...），该可变电阻元件（R11，R12 ...） 第一电极和第二电极，以及包括放置在第三电极和第四电极之间并与第三电极和第四电极接触的电流导向层的电流导向元件（D11，D12 ...）串联连接，并且驱动该装置 通过第一LR驱动电路（105a1）经由限流电路（105b），以在器件被第二HR驱动电路（105a2）驱动时降低可变电阻元件的电阻，以增加可变电阻元件的电阻，从而使用 电流限制电路（105b），用于使可变电阻元件的电阻降低的电流低于用于增加可变电阻元件的电阻的电流。
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9.发明授权Memory circuit having a crosstalk-glitch suppressor circuit and a control device for controlling an amount of suppression performed by the crosstalk-glitch suppressor circuit 有权具有串扰毛刺抑制电路的记忆电路和用于控制由串扰毛刺抑制电路执行的抑制量的控制装置公开(公告)号：US07509607B2
公开(公告)日：2009-03-24
申请号：US11304775
申请日：2005-12-16
申请人： Yuuichirou Ikeda
发明人： Yuuichirou Ikeda
CPC分类号： G11C29/02 , G11C7/02 , G11C7/1048 , G11C8/08 , G11C2029/5002
摘要： The memory circuit comprises: a single or a plurality of reading-out port(s); a single or a plurality of writing port(s); a crosstalk-glitch suppressor circuit for suppressing crosstalk glitch between internal signal lines of each of the ports; and a control device for controlling capacity of the crosstalk-glitch suppressor circuit.
摘要翻译： 存储电路包括：单个或多个读出端口; 一个或多个书写口; 用于抑制每个端口的内部信号线之间的串扰毛刺的串扰毛刺抑制电路; 以及用于控制串扰毛刺抑制电路的容量的控制装置。
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公开(公告)号：US20070103954A1
公开(公告)日：2007-05-10
申请号：US11590803
申请日：2006-11-01
申请人： Yuuichirou Ikeda
发明人： Yuuichirou Ikeda
IPC分类号： G11C5/02
CPC分类号： G11C11/412 , G11C5/143
摘要： There is provided a memory circuit including a first memory cell mapped on an address space accessible from a processor, and a second memory cell not mapped on the address space and having the same constitution as that of the first memory cell, wherein a control circuit for executing a control function relating to the memory circuit is included, and an output signal line of the second memory cell is connected to the control circuit.
摘要翻译： 提供了一种存储电路，其包括映射在可从处理器访问的地址空间的第一存储器单元和未映射到地址空间上并具有与第一存储单元相同构造的第二存储单元，其中控制电路用于 包括执行与存储器电路相关的控制功能，并且第二存储单元的输出信号线连接到控制电路。
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