公开(公告)号：US07057419B2

公开(公告)日：2006-06-06

申请号：US10495989

申请日：2002-07-30

申请人： Yasuhito Takeo ,  Nobuhiro Toyoda ,  Masatoshi Tobayashi

发明人： Yasuhito Takeo ,  Nobuhiro Toyoda ,  Masatoshi Tobayashi

IPC分类号： G01R23/02

CPC分类号： H03L7/087 ,  H03L7/091 ,  H03L7/113 ,  H03L7/235 ,  H04L7/033

摘要： In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comparison circuit (10), a phase sync circuit (40) capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit (10) to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D. This logical value is fed back by a frequency comparison loop F2 to bring the frequency of the clock signal CK close to the bit rate of the data signal D without requiring any reference clock signal, thus achieving both broadening of the capture range and extraction of a high-quality clock signal.

摘要翻译： 在以随机NRZ格式从数据信号D提取时钟信号CK的相位同步电路（40）中，特别是在包括相位比较电路（81）和相位比较电路（81）的双回路配置的相位同步电路（40）中， 频率比较电路（10），提供能够实现捕获范围的扩大和提取高质量时钟信号而不需要任何参考时钟信号的相位同步电路（40）。 从时钟信号Ca和数据信号D延迟大约1/4周期的相位的时钟信号Ca被输入到频率比较电路（10），以根据高低关系输出逻辑值 在时钟信号的频率与数据信号D的比特率之间。该逻辑值由频率比较环路F 2反馈，以使得时钟信号CK的频率接近于数据信号D的比特率，而没有 需要任何参考时钟信号，从而实现捕获范围的扩大和高质量时钟信号的提取。

公开(公告)号：US20050008112A1

公开(公告)日：2005-01-13

申请号：US10495989

申请日：2002-07-30

申请人： Yasuhito Takeo ,  Nobuhiro Toyoda ,  Masatoshi Tobayashi

发明人： Yasuhito Takeo ,  Nobuhiro Toyoda ,  Masatoshi Tobayashi

IPC分类号： H03K5/26 ,  H03L7/08 ,  H03L7/087 ,  H03L7/091 ,  H03L7/10 ,  H03L7/113 ,  H03L7/23 ,  H04L7/033 ,  H03D3/24

CPC分类号： H03L7/087 ,  H03L7/091 ,  H03L7/113 ,  H03L7/235 ,  H04L7/033

摘要： In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comparison circuit (10), a phase sync circuit (40) capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit (10) to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D. This logical value is fed back by a frequency comparison loop F2 to bring the frequency of the clock signal CK close to the bit rate of the data signal D without requiring any reference clock signal, thus achieving both broadening of the capture range and extraction of a high-quality clock signal.

摘要翻译： 在以随机NRZ格式从数据信号D提取时钟信号CK的相位同步电路（40）中，特别是在包括相位比较电路（81）和相位比较电路（81）的双回路配置的相位同步电路（40）中， 频率比较电路（10），提供能够实现捕获范围的扩大和提取高质量时钟信号而不需要任何参考时钟信号的相位同步电路（40）。 从时钟信号Ca和数据信号D延迟大约1/4周期的相位的时钟信号Ca被输入到频率比较电路（10），以根据高低关系输出逻辑值 在时钟信号的频率和数据信号D的比特率之间。该逻辑值由频率比较环F2反馈，使得时钟信号CK的频率接近于数据信号D的比特率，而不需要 任何参考时钟信号，从而实现了捕获范围的扩大和高质量时钟信号的提取。