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公开(公告)号：US20080309407A1
公开(公告)日：2008-12-18
申请号：US11658688
申请日：2005-08-03
申请人： Makoto Nakamura , Yohtaro Umeda , Jun Endou , Yuji Akatsu , Yuuki Imsi , Masatoshi Tobayashi , Yoshikazu Urabe , Hatsushi Iizuka , Eiji Hyodo
发明人： Makoto Nakamura , Yohtaro Umeda , Jun Endou , Yuji Akatsu , Yuuki Imsi , Masatoshi Tobayashi , Yoshikazu Urabe , Hatsushi Iizuka , Eiji Hyodo
IPC分类号： H03F3/45
CPC分类号： H03G3/3084 , H03F1/08 , H03F3/087 , H03G1/0088
摘要： A gain switching determination circuit (250) compares/determines a comparative input voltage (Vc) from an inter-stage buffer (230) with a first hysteresis characteristic, and outputs a gain switching signal (SEL) based on the comparison/determination result to first and second transimpedance amplifier core circuits (210, 220), thereby switching the gains of the core circuits. This obviates holding a comparison input voltage with long response time in a level holding circuit for gain switching determination, which allows instantaneous gain switching determination and instantaneous response corresponding to burst data.
摘要翻译： 增益切换确定电路（250）将来自级间缓冲器（230）的比较输入电压（Vc）与第一滞后特性进行比较/确定，并且基于比较/确定结果将增益切换信号（SEL）输出到 第一和第二跨阻放大器核心电路（210,220），从而切换核心电路的增益。 这避免了在用于增益切换确定的电平保持电路中保持具有长响应时间的比较输入电压，这允许对应于突发数据的瞬时增益切换确定和瞬时响应。
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公开(公告)号：US08593223B2
公开(公告)日：2013-11-26
申请号：US13527512
申请日：2012-06-19
申请人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Yasunobu Inabe , Eisuke Tsuchiya
发明人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Yasunobu Inabe , Eisuke Tsuchiya
IPC分类号： H03G3/10
CPC分类号： H03G1/0023
摘要： In an automatic gain control circuit, a peak detection circuit detects and outputs the peak voltage of an output signal from a variable gain circuit. An average value detection/output amplitude setting circuit detects the average value voltage of an output signal from the variable gain circuit, and outputs a calculated voltage. An amplification circuit controls the gain of the variable gain circuit by amplifying the difference between the output voltages of the peak detection circuit and average value detection/output amplitude setting circuit. The number of base-emitter junctions of transistors on a path in the peak detection circuit from input ports which receive output signals from the variable gain circuit to an output port which outputs a voltage to the amplification circuit is equal to the number of base-emitter junctions of transistors on a path in the average value detection/output amplitude setting circuit.
摘要翻译： 在自动增益控制电路中，峰值检测电路检测并输出来自可变增益电路的输出信号的峰值电压。 平均值检测/输出振幅设定电路检测来自可变增益电路的输出信号的平均值电压，并输出计算出的电压。 放大电路通过放大峰值检测电路的输出电压和平均值检测/输出幅度设定电路之间的差来控制可变增益电路的增益。 从输入端口接收峰值检测电路中的路径上的晶体管的基极 - 发射极结数量，该输入端口从可变增益电路接收输出到放大电路的电压的输出端口等于基极 - 发射极 在平均值检测/输出幅度设置电路中的路径上的晶体管的结。
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公开(公告)号：US07868701B2
公开(公告)日：2011-01-11
申请号：US11658688
申请日：2005-08-03
申请人： Makoto Nakamura , Yohtaro Umeda , Jun Endou , Yuji Akatsu , Yuuki Imai , Masatoshi Tobayashi , Yoshikazu Urabe , Hatsushi Iizuka , Eiji Hyodo
发明人： Makoto Nakamura , Yohtaro Umeda , Jun Endou , Yuji Akatsu , Yuuki Imai , Masatoshi Tobayashi , Yoshikazu Urabe , Hatsushi Iizuka , Eiji Hyodo
IPC分类号： H03F3/08
CPC分类号： H03G3/3084 , H03F1/08 , H03F3/087 , H03G1/0088
摘要： A gain switching determination circuit (250) compares/determines a comparative input voltage (Vc) from an inter-stage buffer (230) with a first hysteresis characteristic, and outputs a gain switching signal (SEL) based on the comparison/determination result to first and second transimpedance amplifier core circuits (210, 220), thereby switching the gains of the core circuits. This obviates holding a comparison input voltage with long response time in a level holding circuit for gain switching determination, which allows instantaneous gain switching determination and instantaneous response corresponding to burst data.
摘要翻译： 增益切换确定电路（250）将来自级间缓冲器（230）的比较输入电压（Vc）与第一滞后特性进行比较/确定，并且基于比较/确定结果将增益切换信号（SEL）输出到 第一和第二跨阻放大器核心电路（210,220），从而切换核心电路的增益。 这避免了在用于增益切换确定的电平保持电路中保持具有长响应时间的比较输入电压，这允许对应于突发数据的瞬时增益切换确定和瞬时响应。
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公开(公告)号：US08593201B2
公开(公告)日：2013-11-26
申请号：US13527510
申请日：2012-06-19
申请人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Eisuke Tsuchiya
发明人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Eisuke Tsuchiya
IPC分类号： H03L5/00
CPC分类号： H03K19/017545
摘要： In a signal output circuit, an input buffer externally receives a single-phase switching instruction signal to switch a state of the output circuit a shutdown disable state or a shutdown enable state, and converts and outputs the single-phase switching instruction signal into a differential switching instruction signal. A generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signal. A control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal. An output circuit externally receives a differential input signal, outputs a differential output signal upon impedance-converting the differential input signal, and switches between the shutdown disable state and the shutdown enable state of the differential input signal.
摘要翻译： 在信号输出电路中，输入缓冲器从外部接收单相开关指令信号，以将输出电路的状态切换到关闭禁止状态或关断使能状态，并将单相切换指令信号转换并输出到差分 切换指令信号。 一代控制电路根据差动切换指示信号输出用于控制控制电压产生电路中的控制电压产生的发电控制信号。 控制电压产生电路根据单相切换指令信号的逻辑改变控制电压的值来输出控制电压。 输出电路从外部接收差分输入信号，通过对差分输入信号进行阻抗转换来输出差分输出信号，并在差分输入信号的关断禁止状态和关断使能状态之间切换。
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公开(公告)号：US20070292139A1
公开(公告)日：2007-12-20
申请号：US11659413
申请日：2005-08-02
IPC分类号： H04B10/00
CPC分类号： H03G3/3084 , H03F3/08 , H03F2200/375 , H04B10/6933
摘要： A receiving method according to the present invention adjusts a level of an output voltage signal by switching a gain to be used for converting an inputted current signal to a voltage signal, in a preamplifier. Performing offset compensation on the output voltage signal in an offset compensator, in a post amplifier. Adding a reset signal, whose polarity is made opposite to a polarity of the output voltage signal, to the output voltage signal, in the preamplifier. Detecting the reset signal having added to the output voltage signal, and resetting the offset compensator by use of the detected reset signal, in the post amplifier.
摘要翻译： 根据本发明的接收方法通过在前置放大器中切换用于将输入的电流信号转换为电压信号的增益来调节输出电压信号的电平。 在后置放大器中对偏置补偿器的输出电压信号执行偏移补偿。 将其极性与输出电压信号的极性相反的复位信号添加到前置放大器中的输出电压信号。 检测添加到输出电压信号的复位信号，并通过使用检测到的复位信号在后置放大器中复位偏移补偿器。
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公开(公告)号：US20120326782A1
公开(公告)日：2012-12-27
申请号：US13527512
申请日：2012-06-19
申请人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Yasunobu Inabe , Eisuke Tsuchiya
发明人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Yasunobu Inabe , Eisuke Tsuchiya
IPC分类号： H03G3/20
CPC分类号： H03G1/0023
摘要： In an automatic gain control circuit, a peak detection circuit detects and outputs the peak voltage of an output signal from a variable gain circuit. An average value detection/output amplitude setting circuit detects the average value voltage of an output signal from the variable gain circuit, and outputs a calculated voltage. An amplification circuit controls the gain of the variable gain circuit by amplifying the difference between the output voltages of the peak detection circuit and average value detection/output amplitude setting circuit. The number of base-emitter junctions of transistors on a path in the peak detection circuit from input ports which receive output signals from the variable gain circuit to an output port which outputs a voltage to the amplification circuit is equal to the number of base-emitter junctions of transistors on a path in the average value detection/output amplitude setting circuit.
摘要翻译： 在自动增益控制电路中，峰值检测电路检测并输出来自可变增益电路的输出信号的峰值电压。 平均值检测/输出振幅设定电路检测来自可变增益电路的输出信号的平均值电压，并输出计算出的电压。 放大电路通过放大峰值检测电路的输出电压和平均值检测/输出幅度设定电路之间的差来控制可变增益电路的增益。 从输入端口接收峰值检测电路中的路径上的晶体管的基极 - 发射极结数量，该输入端口从可变增益电路接收输出到放大电路的电压的输出端口等于基极 - 发射极 在平均值检测/输出幅度设置电路中的路径上的晶体管的结。
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公开(公告)号：US20120319766A1
公开(公告)日：2012-12-20
申请号：US13527510
申请日：2012-06-19
申请人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Eisuke Tsuchiya
发明人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Eisuke Tsuchiya
IPC分类号： G05F3/02
CPC分类号： H03K19/017545
摘要： In a signal output circuit, an input buffer externally receives a single-phase switching instruction signal to switch a state of the output circuit a shutdown disable state or a shutdown enable state, and converts and outputs the single-phase switching instruction signal into a differential switching instruction signal. A generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signal. A control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal. An output circuit externally receives a differential input signal, outputs a differential output signal upon impedance-converting the differential input signal, and switches between the shutdown disable state and the shutdown enable state of the differential input signal.
摘要翻译： 在信号输出电路中，输入缓冲器从外部接收单相开关指令信号，以将输出电路的状态切换到关闭禁止状态或关断使能状态，并将单相切换指令信号转换并输出到差分 切换指令信号。 一代控制电路根据差动切换指示信号输出用于控制控制电压产生电路中的控制电压产生的发电控制信号。 控制电压产生电路根据单相切换指令信号的逻辑改变控制电压的值来输出控制电压。 输出电路从外部接收差分输入信号，通过对差分输入信号进行阻抗转换来输出差分输出信号，并在差分输入信号的关断禁止状态和关断使能状态之间切换。
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公开(公告)号：US08144813B2
公开(公告)日：2012-03-27
申请号：US11659413
申请日：2005-08-02
IPC分类号： H04L25/06
CPC分类号： H03G3/3084 , H03F3/08 , H03F2200/375 , H04B10/6933
摘要： A receiving method according to the present invention adjusts a level of an output voltage signal by switching a gain to be used for converting an inputted current signal to a voltage signal, in a preamplifier. Performing offset compensation on the output voltage signal in an offset compensator, in a post amplifier. Adding a reset signal, whose polarity is made opposite to a polarity of the output voltage signal, to the output voltage signal, in the preamplifier. Detecting the reset signal having added to the output voltage signal, and resetting the offset compensator by use of the detected reset signal, in the post amplifier.
摘要翻译： 根据本发明的接收方法通过在前置放大器中切换用于将输入的电流信号转换为电压信号的增益来调节输出电压信号的电平。 在后置放大器中对偏置补偿器的输出电压信号执行偏移补偿。 将其极性与输出电压信号的极性相反的复位信号添加到前置放大器中的输出电压信号。 检测添加到输出电压信号的复位信号，并通过使用检测到的复位信号在后置放大器中复位偏移补偿器。
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公开(公告)号：US07057419B2
公开(公告)日：2006-06-06
申请号：US10495989
申请日：2002-07-30
IPC分类号： G01R23/02
摘要： In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comparison circuit (10), a phase sync circuit (40) capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit (10) to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D. This logical value is fed back by a frequency comparison loop F2 to bring the frequency of the clock signal CK close to the bit rate of the data signal D without requiring any reference clock signal, thus achieving both broadening of the capture range and extraction of a high-quality clock signal.
摘要翻译： 在以随机NRZ格式从数据信号D提取时钟信号CK的相位同步电路（40）中，特别是在包括相位比较电路（81）和相位比较电路（81）的双回路配置的相位同步电路（40）中， 频率比较电路（10），提供能够实现捕获范围的扩大和提取高质量时钟信号而不需要任何参考时钟信号的相位同步电路（40）。 从时钟信号Ca和数据信号D延迟大约1/4周期的相位的时钟信号Ca被输入到频率比较电路（10），以根据高低关系输出逻辑值 在时钟信号的频率与数据信号D的比特率之间。该逻辑值由频率比较环路F 2反馈，以使得时钟信号CK的频率接近于数据信号D的比特率，而没有 需要任何参考时钟信号，从而实现捕获范围的扩大和高质量时钟信号的提取。
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公开(公告)号：US06888379B2
公开(公告)日：2005-05-03
申请号：US10088205
申请日：2001-10-11
CPC分类号： H03L7/085 , H03D13/008 , H04L7/0331
摘要： A phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and has a high linearity of a phase to voltage conversion characteristic around a phase-locked point in an operation of comparing phases of random NRZ signals in a phase. By using the phase detector circuit having a circuit configuration containing a delay circuit and a combination of leapt a multiplier circuit and a subtractor circuit, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminal 3 of a multiplier circuit 62 approaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and thus high linearity of the phase to voltage conversion characteristic around thus phase-locked point can be realized.
摘要翻译： 一种相位检测器电路，其防止在输入CID（连续相同位）期间显着的锁定损失，并且在比较相位锁定点周围的随机NRZ信号的相位的操作中具有高线性度的相位 - 电压转换特性 相。 通过使用具有包含延迟电路的电路结构的相位检测器电路和倍增乘法器电路和减法器电路的组合，可以实现防止锁定显着损失的PLL电路的能力。 此外，由于接近乘法器电路62的输出端3处的脉冲的占空比接近50％，因此不会出现相电压转换特性的失真，因此高线性 的相位锁定点之间的相电压转换特性可以实现。
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