公开(公告)号：US20120139087A1

公开(公告)日：2012-06-07

申请号：US13305418

申请日：2011-11-28

申请人： Yasuki YOSHIHISA ,  Tetsuya NITTA

发明人： Yasuki YOSHIHISA ,  Tetsuya NITTA

IPC分类号： H01L29/02

CPC分类号： H01L27/088 ,  H01L21/823481 ,  H01L27/0248

摘要： The semiconductor device includes: a semiconductor substrate; a pair of injection elements; an active barrier structure; and a p-type ground region. The semiconductor substrate has a main surface and a p-type region formed therein. The active barrier structure is arranged in a region sandwiched between the pair of injection elements over the main surface. The p-type ground region is a ground potential-applicable region which is formed closer to an end side of the main surface than the pair of injection elements and the active barrier structure, bypassing a region sandwiched between the pair of injection elements over the main surface, and which is electrically coupled to the p-type region. The p-type ground region is divided by a region adjacent to the region sandwiched between the pair of injection elements.

摘要翻译： 半导体器件包括：半导体衬底; 一对注射元件; 主动屏障结构; 和p型接地区域。 半导体衬底具有形成在其中的主表面和p型区域。 主动屏障结构布置在主表面上夹在该对注入元件之间的区域中。 所述p型接地区域是形成为比所述一对注入元件和所述有源势垒结构更接近所述主面的端侧的接地电位适用区域，所述区域绕着所述一对注入元件之间夹在所述主体 表面，并且其电耦合到p型区域。 p型接地区域被夹在一对注入元件之间的区域相邻的区域划分。

公开(公告)号：US20110284987A1

公开(公告)日：2011-11-24

申请号：US13110630

申请日：2011-05-18

申请人： Yasuki YOSHIHISA ,  Kikuo KATO ,  Tetsuya NITTA ,  Kazuma ONISHI

发明人： Yasuki YOSHIHISA ,  Kikuo KATO ,  Tetsuya NITTA ,  Kazuma ONISHI

IPC分类号： H01L29/06

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L27/0251 ,  H01L27/088

摘要： There is provided a semiconductor device capable of suppressing malfunction of an element to be protected, caused by electrons from an output element into a semiconductor substrate. The semiconductor device is provided with the semiconductor substrate, the output element, the element to be protected, a tap part, and a first active-barrier structure. The first active-barrier structure is disposed between the element to be protected and the tap part. Further, the first active-barrier structure includes an n-type region joined with a p-type doped region, and a p-type region in ohmic coupling with the n-type region.

摘要翻译： 提供一种半导体器件，其能够抑制从输出元件到半导体衬底的电子引起的被保护元件的故障。 半导体器件设置有半导体衬底，输出元件，要保护的元件，抽头部件和第一有源屏障结构。 第一主动阻挡结构设置在待保护元件与抽头部件之间。 此外，第一有源屏障结构包括与p型掺杂区域连接的n型区域和与n型区域欧姆耦合的p型区域。

公开(公告)号：US20110175205A1

公开(公告)日：2011-07-21

申请号：US13010417

申请日：2011-01-20

申请人： Katsumi MORII ,  Yoshitaka OTSU ,  Kazuma ONISHI ,  Tetsuya NITTA ,  Tatsuya SHIROMOTO ,  Shigeo TOKUMITSU

发明人： Katsumi MORII ,  Yoshitaka OTSU ,  Kazuma ONISHI ,  Tetsuya NITTA ,  Tatsuya SHIROMOTO ,  Shigeo TOKUMITSU

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L21/76283 ,  H01L21/76232 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.

摘要翻译： 提供可以使用简单的工艺制造而不确保高嵌入性的半导体器件; 以及该装置的制造方法。 在根据本发明的半导体器件的制造方法中，首先准备具有通过堆叠支撑衬底，埋入绝缘膜和半导体层获得的构造的半导体衬底。 然后，在半导体层的主表面上完成具有导电部分的元件。 形成了在平面图中包围元件并从半导体层的主表面到达掩埋绝缘膜的沟槽。 在元件上和沟槽中形成第一绝缘膜（层间绝缘膜）以覆盖元件并分别在沟槽中形成气隙。 然后，在第一绝缘膜中形成到达元件的导电部分的接触孔。

公开(公告)号：US20110198726A1

公开(公告)日：2011-08-18

申请号：US13095352

申请日：2011-04-27

申请人： Tetsuya NITTA ,  Takayuki Igarashi

发明人： Tetsuya NITTA ,  Takayuki Igarashi

IPC分类号： H01L29/735

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/761 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7317 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/8611

摘要： An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N− layer. Between trench isolation region and the N− layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N− layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

摘要翻译： 在半导体衬底上形成有一个BOX层的N层。 在N层中，形成沟槽隔离区域以包围N层以成为元件形成区域。 沟槽隔离区形成为从N层的表面到达BOX层。 在沟槽隔离区域和N层之间形成P型扩散区域10a。 连续形成P型扩散区域而不间断地与围绕元件形成区域的沟槽隔离区域的内侧壁的整个表面接触。 在N层的元件形成区域中，形成规定的半导体元件。 因此，形成了可靠地建立电绝缘的半导体器件，而不增加元件形成区域占据的面积。