公开(公告)号：US08345480B2

公开(公告)日：2013-01-01

申请号：US13305532

申请日：2011-11-28

申请人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

发明人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

IPC分类号： G11C11/34

CPC分类号： G09G3/3655 ,  G09G5/005 ,  G09G2310/08 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.

摘要翻译： 本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设置驱动条件等。 在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。 存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

公开(公告)号：US08089810B2

公开(公告)日：2012-01-03

申请号：US12890642

申请日：2010-09-25

申请人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

发明人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

IPC分类号： G11C11/34

CPC分类号： G09G3/3655 ,  G09G5/005 ,  G09G2310/08 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.

摘要翻译： 本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设定驱动条件等。 在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。 存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

公开(公告)号：US20120069670A1

公开(公告)日：2012-03-22

申请号：US13305532

申请日：2011-11-28

申请人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

发明人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

IPC分类号： G11C11/34

CPC分类号： G09G3/3655 ,  G09G5/005 ,  G09G2310/08 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.

摘要翻译： 本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设置驱动条件等。 在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。 存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

公开(公告)号：US20110012906A1

公开(公告)日：2011-01-20

申请号：US12890642

申请日：2010-09-25

申请人： Yasushi KAWASE ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

发明人： Yasushi KAWASE ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

IPC分类号： G06F12/02

CPC分类号： G09G3/3655 ,  G09G5/005 ,  G09G2310/08 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.

摘要翻译： 本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设定驱动条件等。 在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。 存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

公开(公告)号：US07826264B2

公开(公告)日：2010-11-02

申请号：US11441166

申请日：2006-05-26

申请人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

发明人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

IPC分类号： G11C11/34

CPC分类号： G09G3/3655 ,  G09G5/005 ,  G09G2310/08 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.

摘要翻译： 本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设定驱动条件等。 在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。 存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。

公开(公告)号：US20060267903A1

公开(公告)日：2006-11-30

申请号：US11441166

申请日：2006-05-26

申请人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

发明人： Yasushi Kawase ,  Susumu Ishida ,  Takesada Akiba ,  Yasushi Nagata ,  Naoki Miyamoto ,  Kazuyoshi Shiba

IPC分类号： G09G3/36

CPC分类号： G09G3/3655 ,  G09G5/005 ,  G09G2310/08 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.

公开(公告)号：US20090209078A1

公开(公告)日：2009-08-20

申请号：US12432393

申请日：2009-04-29

申请人： Hideki YASUOKA ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

发明人： Hideki YASUOKA ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/092 ,  Y10S438/981

摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.

摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。

公开(公告)号：US07790554B2

公开(公告)日：2010-09-07

申请号：US12432393

申请日：2009-04-29

申请人： Hideki Yasuoka ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

发明人： Hideki Yasuoka ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

IPC分类号： H01L21/77

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/092 ,  Y10S438/981

摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.

摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。

公开(公告)号：US20100034811A1

公开(公告)日：2010-02-11

申请号：US12161733

申请日：2007-01-26

申请人： Susumu Ishida

发明人： Susumu Ishida

IPC分类号： A61K39/395 ,  A61P27/02

CPC分类号： C07K16/2866 ,  A61K2039/505

摘要： The present inventors focused on the fact that inflammation at the subretinal macular area enhances choroidal neovascularization, and developed pharmaceutical agents that suppress initiation or advancement of neovascularization by angiogenic factors such as VEGF. More specifically, the present inventors revealed that administering anti-IL-6 receptor monoclonal antibodies to mice treated with laser photocoagulation inhibits the development of choroidal neovascularization.

摘要翻译： 本发明人着眼于视网膜下黄斑区域的炎症增强脉络膜新生血管形成，并开发出通过血管生成因子如VEGF抑制新生血管形成的进展的药剂。 更具体地，本发明人揭示了对用激光凝固治疗的小鼠施用抗IL-6受体单克隆抗体抑制了脉络膜新血管形成的发展。

公开(公告)号：US07541661B2

公开(公告)日：2009-06-02

申请号：US11614469

申请日：2006-12-21

申请人： Hideki Yasuoka ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

发明人： Hideki Yasuoka ,  Masami Kouketsu ,  Susumu Ishida ,  Kazunari Saitou

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/092 ,  Y10S438/981

摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.

摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。