公开(公告)号：US20060087887A1

公开(公告)日：2006-04-27

申请号：US11235206

申请日：2005-09-27

申请人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawal

发明人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawal

IPC分类号： G11C16/06

CPC分类号： G11C16/102

摘要： The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

摘要翻译： 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US20080043531A1

公开(公告)日：2008-02-21

申请号：US11849891

申请日：2007-09-04

申请人： Yasushi KAMEDA ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

发明人： Yasushi KAMEDA ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC分类号： G11C16/06

CPC分类号： G11C16/102

摘要： The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

摘要翻译： 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US07729178B2

公开(公告)日：2010-06-01

申请号：US11849891

申请日：2007-09-04

申请人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

发明人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC分类号： G11C7/10

CPC分类号： G11C16/102

摘要： The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

摘要翻译： 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US07327616B2

公开(公告)日：2008-02-05

申请号：US11235206

申请日：2005-09-27

申请人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

发明人： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC分类号： G11C5/14

CPC分类号： G11C16/102

摘要： The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

摘要翻译： 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US07352625B2

公开(公告)日：2008-04-01

申请号：US11196445

申请日：2005-08-04

申请人： Takuya Futatsuyama ,  Ken Takeuchi

发明人： Takuya Futatsuyama ,  Ken Takeuchi

IPC分类号： G11C11/34

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483

摘要： A semiconductor memory device disclosed herein includes: a first select gate line, a gate electrode of a first select transistor connected to the first select gate line; a second select gate line, a gate electrode of a second select transistor connected to the second select gate line; and word lines between the first select gate line and the second select gate line, gate electrodes of memory cells being respectively connected to the word lines, wherein when data in a memory cell connected to a first adjacent word line which is adjacent to the first select gate line is read, a voltage of the second select gate line is increased after a voltage of the first select gate line is increased, and when data in a memory cell connected to a second adjacent word line adjacent to the second select gate line is read, the voltage of the first select gate line is increased after the voltage of the second gate line is increased.

摘要翻译： 本文公开的半导体存储器件包括：第一选择栅极线，连接到第一选择栅极线的第一选择晶体管的栅电极; 第二选择栅极线，连接到第二选择栅极线的第二选择晶体管的栅电极; 和第一选择栅极线与第二选择栅极线之间的字线，存储单元的栅电极分别连接到字线，其中当连接到与第一选择栅极相邻的第一相邻字线的存储单元中的数据时 在第一选择栅极线的电压增加之后第二选择栅极线的电压被增加，并且当连接到与第二选择栅极线相邻的第二相邻字线的存储单元中的数据被读取时，第二选择栅极线的电压被增加 在第二栅极线的电压增加之后第一选择栅极线的电压增加。

公开(公告)号：US07274603B2

公开(公告)日：2007-09-25

申请号：US11330143

申请日：2006-01-12

申请人： Takuya Futatsuyama ,  Ken Takeuchi

发明人： Takuya Futatsuyama ,  Ken Takeuchi

IPC分类号： G11C7/00

CPC分类号： G11C16/08 ,  G11C16/0483 ,  H03K19/01855

摘要： A level shifter circuit comprises a first output MIS transistor of a first conductivity, and a second output MIS transistor of a second conductivity type having a second threshold voltage. The former has a first threshold voltage, wherein the output voltage is positively fed back to a gate terminal and the power supply voltage is applied to a first terminal to generate a first voltage at a second terminal. In the latter, the first voltage is applied to a first terminal and a second voltage is applied to a gate terminal to control conduction to generate the output voltage at a second terminal. The first and second charge type MIS transistors and the discharge MIS transistor are connected between the first terminal and gate terminal of the second output MIS transistor to charge or discharge the potential of the gate terminal of the second output MIS transistor.

摘要翻译： 电平移位器电路包括具有第一导电率的第一输出MIS晶体管和具有第二阈值电压的第二导电类型的第二输出MIS晶体管。 前者具有第一阈值电压，其中输出电压被正向反馈到栅极端子，并且将电源电压施加到第一端子以在第二端子处产生第一电压。 在后者中，第一电压被施加到第一端子，并且第二电压被施加到栅极端子以控制导通以在第二端子处产生输出电压。 第一和第二充电型MIS晶体管和放电MIS晶体管连接在第二输出MIS晶体管的第一端子和栅极端子之间，以对第二输出MIS晶体管的栅极端子的电位进行充电或放电。

公开(公告)号：US20060072359A1

公开(公告)日：2006-04-06

申请号：US11196445

申请日：2005-08-04

申请人： Takuya Futatsuyama ,  Ken Takeuchi

发明人： Takuya Futatsuyama ,  Ken Takeuchi

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483

摘要： A semiconductor memory device disclosed herein includes: a first select gate line, a gate electrode of a first select transistor connected to the first select gate line; a second select gate line, a gate electrode of a second select transistor connected to the second select gate line; and word lines between the first select gate line and the second select gate line, gate electrodes of memory cells being respectively connected to the word lines, wherein when data in a memory cell connected to a first adjacent word line which is adjacent to the first select gate line is read, a voltage of the second select gate line is increased after a voltage of the first select gate line is increased, and when data in a memory cell connected to a second adjacent word line adjacent to the second select gate line is read, the voltage of the first select gate line is increased after the voltage of the second gate line is increased.

摘要翻译： 本文公开的半导体存储器件包括：第一选择栅极线，连接到第一选择栅极线的第一选择晶体管的栅电极; 第二选择栅极线，连接到第二选择栅极线的第二选择晶体管的栅电极; 和第一选择栅极线与第二选择栅极线之间的字线，存储单元的栅电极分别连接到字线，其中当连接到与第一选择栅极相邻的第一相邻字线的存储单元中的数据时 在第一选择栅极线的电压增加之后第二选择栅极线的电压被增加，并且当连接到与第二选择栅极线相邻的第二相邻字线的存储单元中的数据被读取时，第二选择栅极线的电压被增加 在第二栅极线的电压增加之后第一选择栅极线的电压增加。

公开(公告)号：US20070036016A1

公开(公告)日：2007-02-15

申请号：US11531082

申请日：2006-09-12

申请人： Ken Takeuchi ,  Takuya Futatsuyama ,  Koichi Kawai

发明人： Ken Takeuchi ,  Takuya Futatsuyama ,  Koichi Kawai

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/105

摘要： A nonvolatile semiconductor memory device includes a memory cell array, read circuit, program circuit, read voltage generating circuit, memory circuit and switching circuit. The read voltage generating circuit generates and supplies a read voltage to the read circuit. The memory circuit stores information which changes the temperature characteristic of a memory cell in the memory cell array. The switching circuit changes the temperature dependency of read voltage generated from the read voltage generating circuit based on information stored in the memory circuit.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，读取电路，程序电路，读取电压产生电路，存储器电路和开关电路。 读取电压产生电路产生读取电压并将读取电压提供给读取电路。 存储电路存储改变存储单元阵列中的存储单元的温度特性的信息。 开关电路基于存储在存储器电路中的信息改变从读取电压产生电路产生的读取电压的温度依赖性。

公开(公告)号：US07411830B2

公开(公告)日：2008-08-12

申请号：US11531082

申请日：2006-09-12

申请人： Ken Takeuchi ,  Takuya Futatsuyama ,  Koichi Kawai

发明人： Ken Takeuchi ,  Takuya Futatsuyama ,  Koichi Kawai

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/105

摘要： A nonvolatile semiconductor memory device includes a memory cell array, read circuit, program circuit, read voltage generating circuit, memory circuit and switching circuit. The read voltage generating circuit generates and supplies a read voltage to the read circuit. The memory circuit stores information which changes the temperature characteristic of a memory cell in the memory cell array. The switching circuit changes the temperature dependency of read voltage generated from the read voltage generating circuit based on information stored in the memory circuit.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，读取电路，程序电路，读取电压产生电路，存储器电路和开关电路。 读取电压产生电路产生读取电压并将读取电压提供给读取电路。 存储电路存储改变存储单元阵列中的存储单元的温度特性的信息。 开关电路基于存储在存储器电路中的信息改变从读取电压产生电路产生的读取电压的温度依赖性。

公开(公告)号：US20060186942A1

公开(公告)日：2006-08-24

申请号：US11330143

申请日：2006-01-12

申请人： Takuya Futatsuyama ,  Ken Takeuchi

发明人： Takuya Futatsuyama ,  Ken Takeuchi

IPC分类号： H03L5/00

CPC分类号： G11C16/08 ,  G11C16/0483 ,  H03K19/01855

摘要： A level shifter circuit comprises a first output MIS transistor of a first conductivity, and a second output MIS transistor of a second conductivity type having a second threshold voltage. The former has a first threshold voltage, wherein the output voltage is positively fed back to a gate terminal and the power supply voltage is applied to a first terminal to generate a first voltage at a second terminal. In the latter, the first voltage is applied to a first terminal and a second voltage is applied to a gate terminal to control conduction to generate the output voltage at a second terminal. The first and second charge type MIS transistors and the discharge MIS transistor are connected between the first terminal and gate terminal of the second output MIS transistor to charge or discharge the potential of the gate terminal of the second output MIS transistor.

摘要翻译： 电平移位器电路包括具有第一导电率的第一输出MIS晶体管和具有第二阈值电压的第二导电类型的第二输出MIS晶体管。 前者具有第一阈值电压，其中输出电压被正向反馈到栅极端子，并且将电源电压施加到第一端子以在第二端子处产生第一电压。 在后者中，第一电压被施加到第一端子，并且第二电压被施加到栅极端子以控制导通以在第二端子处产生输出电压。 第一和第二充电型MIS晶体管和放电MIS晶体管连接在第二输出MIS晶体管的第一端子和栅极端子之间，以对第二输出MIS晶体管的栅极端子的电位进行充电或放电。