公开(公告)号：US08049267B2

公开(公告)日：2011-11-01

申请号：US12479473

申请日：2009-06-05

Applicant: Kikuko Sugimae ,  Yasushi Kameda

Inventor： Kikuko Sugimae ,  Yasushi Kameda

IPC: H01L29/788 ,  G11C11/34

CPC classification number: G11C16/08 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/78 ,  H01L29/7831 ,  H01L29/7881

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the substrate, a first gate electrode formed on the gate insulating film, source and drain regions formed in the substrate so as to sandwich the first gate electrode, an intergate insulating film formed on the first gate electrode and including an opening, a second gate electrode formed on the intergate insulating film and electrically connected to the first gate electrode through the opening, and a boost electrode formed on the intergate insulating film and electrically isolated from the first gate electrode and the second gate electrode.

Abstract translation: 半导体器件包括半导体衬底，形成在衬底上的栅极绝缘膜，形成在栅极绝缘膜上的第一栅极电极，形成在衬底中的源极和漏极区域，以夹持第一栅电极，形成栅极间绝缘膜 在第一栅电极上并且包括开口，形成在栅间绝缘膜上并通过开口电连接到第一栅电极的第二栅电极和形成在栅间绝缘膜上并与第一栅极电隔离的升压电极 和第二栅电极。

公开(公告)号：US20080043531A1

公开(公告)日：2008-02-21

申请号：US11849891

申请日：2007-09-04

Applicant: Yasushi KAMEDA ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

Inventor： Yasushi KAMEDA ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC: G11C16/06

CPC classification number: G11C16/102

Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US07236401B2

公开(公告)日：2007-06-26

申请号：US11242897

申请日：2005-10-05

Applicant: Yasushi Kameda

Inventor： Yasushi Kameda

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/3454 ,  G11C16/0483 ,  G11C16/24

Abstract: A nonvolatile semiconductor memory device includes write/verify circuits, a switching elements which divides the bit lines into plural portions, and a control circuit. The control circuit is configured to control the write/verify circuits and switching elements. The control circuit performs a control operation to perform the write and verify operations with the switching elements set in an OFF state when a memory cell of an address to be written lies on the write/verify circuit side in the memory cell array, write and save data into a memory cell lying on the write/verify circuit side with the switching elements set in the OFF state when the memory cell lies farther apart from the write/verify circuit than the switching elements, and then turn ON the switching elements while the write/verify circuit is not being operated and write the saved data into a memory cell of an address to be written.

Abstract translation: 非易失性半导体存储器件包括写/验证电路，将位线分成多个部分的开关元件和控制电路。 控制电路被配置为控制写入/验证电路和开关元件。 当要写入的地址的存储单元位于存储单元阵列中的写入/验证电路侧时，控制电路执行写入和验证操作，其中开关元件设置为OFF状态，写入和保存 当存储单元离开写入/验证电路比开关元件更远离时，开关元件设置在OFF状态下的数据进入位于写入/验证电路侧的存储器单元，然后在写入时接通开关元件 /验证电路未被操作，并将保存的数据写入要写入地址的存储单元。

公开(公告)号：US06442009B1

公开(公告)日：2002-08-27

申请号：US09604720

申请日：2000-06-28

Applicant: Yasushi Kameda ,  Makoto Segawa

Inventor： Yasushi Kameda ,  Makoto Segawa

IPC: H02H900

CPC classification number: G11C29/50 ,  H02H9/046

Abstract: A semiconductor device has an internal circuit (2), a PAD, a NMOS Tr (QN) as a protective transistor formed between a node (N) on a signal line and a first power source (Vss), and a NOR gate (G1) as a logical gate connected to a gate as a control terminal of the NMOS transistor (QN). The internal circuit (2) is connected to the PAD through the signal line. The NOR gate (G1) keeps the protective transistor (QN) an OFF state during a normal operation of the internal circuit (2). In addition, the semiconductor device further includes a test circuit (21). The output from the NOR gate (G1), whose one input is the output from the test circuit (21), is supplied to the gate of the NMOS transistor (QN). The output from the test circuit (21) is thereby output to outside through the NMOS transistor (QN) and the PAD.

Abstract translation: 半导体器件具有形成在信号线上的节点（N）和第一电源（Vss）之间的作为保护晶体管的内部电路（2），PAD，NMOS Tr（QN）以及NOR门（G1） ）作为连接到作为NMOS晶体管（QN）的控制端的栅极的逻辑栅极。 内部电路（2）通过信号线连接到PAD。 NOR门（G1）在内部电路（2）的正常工作期间保持保护晶体管（QN）为OFF状态。 另外，半导体器件还包括测试电路（21）。 来自测试电路（21）的输出端的NOR门（G1）的输出被提供给NMOS晶体管（QN）的栅极。 因此，测试电路（21）的输出通过NMOS晶体管（QN）和PAD输出到外部。

公开(公告)号：US06429454B2

公开(公告)日：2002-08-06

申请号：US09877788

申请日：2001-06-11

Applicant: Hiroshi Hatada ,  Nobuaki Otsuka ,  Osamu Hirabayashi ,  Yasushi Kameda

Inventor： Hiroshi Hatada ,  Nobuaki Otsuka ,  Osamu Hirabayashi ,  Yasushi Kameda

IPC: A01L2358

CPC classification number: G01R31/318538 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has pads that are arranged in such a manner as to easily accept manual needles to carry out a test. This technique is applicable to carry out a test with use of a boundary scan test circuit in synchronization with a cycle time defined by a normal operation clock signal. The semiconductor device has a first pad connected to a first one of registers that form a serial scan chain, to supply test data to the registers, a second pad connected to a last one of the registers, and a third pad to supply a test clock signal to the registers. The registers are arranged in a central part of the semiconductor device, and the first to third pads are arranged at the periphery of the semiconductor device.

Abstract translation: 半导体器件具有以容易接受手动针进行测试的方式布置的垫。 该技术适用于与由正常操作时钟信号定义的周期时间同步地使用边界扫描测试电路进行测试。 半导体器件具有连接到形成串行扫描链的第一个寄存器中的第一焊盘，以将测试数据提供给寄存器，连接到最后一个寄存器的第二焊盘以及提供测试时钟的第三焊盘 信号到寄存器。 寄存器布置在半导体器件的中心部分中，第一至第三焊盘布置在半导体器件的周围。

公开(公告)号：US07266016B2

公开(公告)日：2007-09-04

申请号：US11246215

申请日：2005-10-11

Applicant: Yasushi Kameda

Inventor： Yasushi Kameda

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3459

Abstract: A clamp circuit is connected to one-side ends of first and second bit lines which are adjacent in a memory cell array and a data cache is connected to the other ends thereof. The first and second bit lines are selectively divided into plural portions by use of first and second switching elements. The data cache, clamp circuit and first and second switching elements are controlled by use of a control circuit and the bit line to which a memory cell of an address to be written is connected is precharged by use of the clamp circuit or data cache and the other bit line is shielded by the clamp circuit.

Abstract translation: 钳位电路连接到在存储单元阵列中相邻的第一和第二位线的一端，数据高速缓存与其另一端连接。 通过使用第一和第二开关元件将第一和第二位线选择性地分成多个部分。 通过使用控制电路来控制数据高速缓存，钳位电路和第一和第二开关元件，并且通过使用钳位电路或数据高速缓冲存储器将要写入的地址的存储单元连接到的位线被预充电，并且 其他位线被钳位电路屏蔽。

公开(公告)号：US20060126386A1

公开(公告)日：2006-06-15

申请号：US11242897

申请日：2005-10-05

Applicant: Yasushi Kameda

Inventor： Yasushi Kameda

IPC: G11C16/04

CPC classification number: G11C16/3454 ,  G11C16/0483 ,  G11C16/24

Abstract: A nonvolatile semiconductor memory device includes write/verify circuits, a switching elements which divides the bit lines into plural portions, and a control circuit. The control circuit is configured to control the write/verify circuits and switching elements. The control circuit performs a control operation to perform the write and verify operations with the switching elements set in an OFF state when a memory cell of an address to be written lies on the write/verify circuit side in the memory cell array, write and save data into a memory cell lying on the write/verify circuit side with the switching elements set in the OFF state when the memory cell lies farther apart from the write/verify circuit than the switching elements, and then turn ON the switching elements while the write/verify circuit is not being operated and write the saved data into a memory cell of an address to be written.

Abstract translation: 非易失性半导体存储器件包括写/验证电路，将位线分成多个部分的开关元件和控制电路。 控制电路被配置为控制写入/验证电路和开关元件。 当要写入的地址的存储单元位于存储单元阵列中的写入/验证电路侧时，控制电路执行写入和验证操作，其中开关元件设置为OFF状态，写入和保存 当存储单元离开写入/验证电路比开关元件更远离时，开关元件设置在OFF状态下的数据进入位于写入/验证电路侧的存储器单元，然后在写入时接通开关元件 /验证电路未被操作，并将保存的数据写入要写入地址的存储单元。

公开(公告)号：US20060087887A1

公开(公告)日：2006-04-27

申请号：US11235206

申请日：2005-09-27

Applicant: Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawal

Inventor： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawal

IPC: G11C16/06

CPC classification number: G11C16/102

Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US5751035A

公开(公告)日：1998-05-12

申请号：US718657

申请日：1996-09-23

Applicant: Yasushi Kameda ,  Makoto Segawa

Inventor： Yasushi Kameda ,  Makoto Segawa

IPC: H01L21/822 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11 ,  H01L29/78 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/11 ,  H01L27/1112

Abstract: A semiconductor device is provided with at least one transistor formed on a semiconductor substrate, the transistor being provided with a conductive sidewall spacer, and at least one conductive film formed so as to face a gate of the transistor via an insulative film, the conductive film covering at least an entire region of a gate region of the transistor and acting as a capacitor electrode. The conductive sidewall spacer and the conductive film are connected together. A potential is supplied to the conductive sidewall spacer and the conductive film, the potential being different from a potential of the gate of the transistor.

Abstract translation: 半导体器件设置有形成在半导体衬底上的至少一个晶体管，所述晶体管设置有导电侧壁间隔物，以及至少一个导电膜，其通过绝缘膜形成为面对晶体管的栅极，所述导电膜 覆盖晶体管的栅极区域的至少整个区域并充当电容器电极。 导电侧壁间隔物和导电膜连接在一起。 向导电侧壁间隔物和导电膜提供电位，该电位与晶体管的栅极的电位不同。

公开(公告)号：US5467317A

公开(公告)日：1995-11-14

申请号：US328049

申请日：1994-10-24

Applicant: Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

Inventor： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

IPC: G11C11/41 ,  G11C8/14 ,  G11C11/40 ,  G11C11/34

CPC classification number: G11C8/14

Abstract: A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

Abstract translation: 一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。 主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。 部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。 为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。 为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑 运算结果满足规定的逻辑条件。 每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。 每个主字线连接到第一和第二逆变器的输入端。 各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。 位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。