公开(公告)号：US6157361A

公开(公告)日：2000-12-05

申请号：US892157

申请日：1997-07-14

申请人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

发明人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  H01L27/12 ,  H01L29/78

CPC分类号： G09G3/3674 ,  G09G3/3685 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2310/06 ,  G09G3/20 ,  G09G3/3648 ,  H01L27/12 ,  H01L29/78

摘要： A matrix-type image display device of the present invention is arranged such that image data are selectively applied to pixels arranged in a matrix form through scanning signal lines and data signal lines, and the image data are stored therein, wherein a high potential of a sampling pulse 0V/5V to be output from a logic circuit is shifted to 10 V, and a low potential thereof is shifted to -8 V respectively by first and second level shifters. As a result, a difference between an input signal level from an external circuit such as a control circuit, an image signal processing circuit, etc., and an actual driving signal level of each pixel can be absorbed. Therefore, an additional structure such as an interface circuit, etc., is not needed between the external circuit and the scanning signal line driving circuit, thereby enabling a low cost and a low power consumption.

摘要翻译： 本发明的矩阵型图像显示装置被布置成使得图像数据被选择性地施加到通过扫描信号线和数据信号线以矩阵形式布置的像素，并且图像数据被存储在其中，其中高电位 从逻辑电路输出的采样脉冲0V / 5V被移位到10V，并且其低电位分别由第一和第二电平移位器移位到-8V。 结果，可以吸收来自诸如控制电路的外部电路的输入信号电平，图像信号处理电路等之间的差异和每个像素的实际驱动信号电平之间的差异。 因此，在外部电路和扫描信号线驱动电路之间不需要诸如接口电路等的附加结构，从而能够实现低成本和低功耗。

公开(公告)号：US06465806B2

公开(公告)日：2002-10-15

申请号：US09095587

申请日：1998-06-11

申请人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai ,  Zhang Hongyong ,  Jun Koyama

发明人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai ,  Zhang Hongyong ,  Jun Koyama

IPC分类号： H01L2904

CPC分类号： H01L23/5226 ,  G02F1/1345 ,  G02F1/13454 ,  G09G3/3688 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first conductive layer; an interlayer insulative layer having an opening; and a second conductive layer. The first conductive layer, the interlayer insulative layer and the second conductive layer are sequentially laminated. The opening is partially covered by the second conductive layer, and an area of the first conductive layer is substantially entirely covered by the second conductive layer in the opening.

摘要翻译： 半导体器件包括第一导电层; 具有开口的层间绝缘层; 和第二导电层。 第一导电层，层间绝缘层和第二导电层依次层叠。 开口部分被第二导电层覆盖，并且第一导电层的面积基本上完全被开口中的第二导电层覆盖。

公开(公告)号：US06373460B1

公开(公告)日：2002-04-16

申请号：US09684912

申请日：2000-10-10

申请人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

发明人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

IPC分类号： G09G336

CPC分类号： G09G3/3674 ,  G09G3/20 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2310/06 ,  H01L27/12 ,  H01L29/78

摘要： A matrix-type image display device of the present invention is arranged such that image data are selectively applied to pixels arranged in a matrix form through scanning signal lines and data signal lines, and the image data are stored therein, wherein a high potential of a sampling pulse 0V/5V to be output from a logic circuit is shifted to 10 V, and a low potential thereof is shifted to −8 V respectively by first and second level shifters. As a result, a difference between an input signal level from an external circuit such as a control circuit, an image signal processing circuit, etc., and an actual driving signal level of each pixel can be absorbed. Therefore, an additional structure such as an interface circuit, etc., is not needed between the external circuit and the scanning signal line driving circuit, thereby enabling a low cost and a low power consumption.

摘要翻译： 本发明的矩阵型图像显示装置被布置成使得图像数据被选择性地施加到通过扫描信号线和数据信号线以矩阵形式布置的像素，并且图像数据被存储在其中，其中高电位 从逻辑电路输出的采样脉冲0V / 5V被移位到10V，并且其低电位分别由第一和第二电平移位器移位到-8V。 结果，可以吸收来自诸如控制电路的外部电路的输入信号电平，图像信号处理电路等之间的差异和每个像素的实际驱动信号电平之间的差异。 因此，在外部电路和扫描信号线驱动电路之间不需要诸如接口电路等的附加结构，从而能够实现低成本和低功耗。

公开(公告)号：US06335778B1

公开(公告)日：2002-01-01

申请号：US08901649

申请日：1997-07-28

申请人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

发明人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

IPC分类号： G02F11345

CPC分类号： G09G3/3648 ,  G02F1/13454 ,  G09G3/2074 ,  G09G2300/0408 ,  G09G2310/027

摘要： An active matrix type liquid crystal display device carries out half-tone display with an area gray scale display method, according to which a pixel is composed of a plurality of subpixels and the area of display regions is changed by an image signal that is a binary signal. The amplitude of an opposite electrode is optimized by configuring a data signal line driving circuit with a scanning circuit, latch-in circuits and outputting circuits. This eliminates the needs to externally input an analogue signal and an intermediate voltage, and enables the driving circuit to be configured only with digital circuits. The driving circuit is integrated to prevent increases in cost of the driving circuit and of mounting the driving circuit that are caused by an increase in the number of data signal lines as a result of the adoption of the area gray scale display method. Consequently, it becomes possible to make an attempt to reduce the cost, power consumption and non-defective ratio of the entire system.

摘要翻译： 有源矩阵型液晶显示装置利用区域灰度显示方法进行半色调显示，根据该方式，像素由多个子像素构成，显示区域的区域由二进制图像信号改变 信号。 通过配置具有扫描电路，锁存电路和输出电路的数据信号线驱动电路来优化对置电极的振幅。 这消除了外部输入模拟信号和中间电压的需要，并且使得驱动电路仅被配置为数字电路。 集成了驱动电路，以防止由于采用区域灰度显示方法而导致数据信号线的数量增加而导致的驱动电路的成本增加和驱动电路的安装。 因此，可以尝试降低整个系统的成本，功耗和无缺陷率。

公开(公告)号：US06288699B1

公开(公告)日：2001-09-11

申请号：US09349379

申请日：1999-07-09

申请人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai ,  Hiroshi Yoneda ,  Nobuhiro Kuwabara

发明人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai ,  Hiroshi Yoneda ,  Nobuhiro Kuwabara

IPC分类号： G09G336

CPC分类号： G09G5/008 ,  G09G3/20 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2310/08 ,  H03L7/00

摘要： A delay detecting section detects the phase difference between a first detection signal as a reference and a second detection signal produced by delaying the first detection signal with part of a data signal line driving circuit itself or part of a circuit formed by the same process as the data signal line driving circuit. A phase adjusting section presumes an internal delay of the data signal line driving circuit, and adjusts the phase difference between a clock signal and start signal, and a video signal so that the data signal line driving circuit samples the video signal at an appropriate timing. These structures prevent a lowering of the image quality due to a difference in the timings of the video signal and sampling signal, and provide an image display device capable of displaying a good-quality image with a simple circuit structure.

摘要翻译： 延迟检测部分检测作为基准的第一检测信号和通过用数据信号线驱动电路本身的一部分延迟第一检测信号而产生的第二检测信号或通过与第一检测信号相同的处理形成的电路的一部分来产生的第二检测信号 数据信号线驱动电路。 相位调整部分假设数据信号线驱动电路的内部延迟，并且调整时钟信号和起始信号之间的相位差和视频信号，使得数据信号线驱动电路在适当的定时对视频信号进行采样。 这些结构防止由于视频信号和采样信号的定时的差异导致的图像质量的降低，并且提供能够以简单的电路结构显示优质图像的图像显示装置。

公开(公告)号：US5952854A

公开(公告)日：1999-09-14

申请号：US708503

申请日：1996-09-05

申请人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

发明人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

IPC分类号： G02F1/133 ,  G09G3/36 ,  G11C27/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H03K17/00 ,  H03K17/687 ,  H04N5/66

CPC分类号： G09G3/3688 ,  G09G2300/0417 ,  G09G2310/0294 ,  G09G2320/0247 ,  H01L27/1251

摘要： A sampling circuit for sampling an analog signal in accordance with a timing signal includes a sampling switching element having a CMOS configuration. The sampling switching element includes an n-channel transistor and a p-channel transistor connected in parallel. The drive power and the feedthrough voltage are substantially the same in the n-channel transistor and the p-channel transistor. The sampling circuit, for example, is continued with an image display device.

摘要翻译： 根据定时信号对模拟信号采样的采样电路包括具有CMOS配置的采样开关元件。 采样开关元件包括并联连接的n沟道晶体管和p沟道晶体管。 驱动功率和馈通电压在n沟道晶体管和p沟道晶体管中基本相同。 采样电路例如继续用图像显示装置。

公开(公告)号：US06504522B2

公开(公告)日：2003-01-07

申请号：US09088821

申请日：1998-06-02

申请人： Ichiro Shiraki ,  Yasushi Kubota ,  Tamotsu Sakai

发明人： Ichiro Shiraki ,  Yasushi Kubota ,  Tamotsu Sakai

IPC分类号： G09G320

CPC分类号： G09G3/2011 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2330/021

摘要： An active-matrix-type image display device having a gray-scale power supply for generating gray-scale voltages of different levels, and a source driver that applies gray-scale voltages according to a digital picture signal to source lines and includes one scanning circuit for each source line. The outputs of the scanning circuits are sequentially made active once in a horizontal period. A latch circuit fetches the digital picture signal in synchronization with making the output of the scanning circuit active. The digital picture signal is decoded by a decoder circuit, and one of analog switches becomes a conducting state according to the decoded signal. As a result, one of the gray-scale voltages is output to the source line.

摘要翻译： 一种具有用于产生不同电平的灰度电压的灰度电源的有源矩阵型图像显示装置，以及根据数字图像信号向源极线施加灰度电压的源极驱动器，并且包括一个扫描电路 对于每个源代码行。 扫描电路的输出在水平周期中依次被激活一次。 锁存电路与使扫描电路的输出有效的同步取出数字图像信号。 数字图像信号由解码器电路解码，并且模拟开关中的一个根据解码信号变为导通状态。 结果，其中一个灰度电压被输出到源极线。

公开(公告)号：US06437768B1

公开(公告)日：2002-08-20

申请号：US09060732

申请日：1998-04-15

申请人： Yasushi Kubota ,  Tamotsu Sakai ,  Ichiro Shiraki

发明人： Yasushi Kubota ,  Tamotsu Sakai ,  Ichiro Shiraki

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021

摘要： A shift register circuit, composed of a plurality of serially connected latch circuits, for sequentially transmitting a pulse signal in sync with a rising and a falling of a clock signal, and an output circuit for sequentially outputting a video signal to data signal lines in sync with the pulse signal outputted from the shift register circuit are provided. The shift register circuit is divided into a plurality of latch circuit groups, and the stage numbers of the latch circuits in each latch circuit group is set in such a manner to minimize the time difference between the pulse signal outputted from each latch circuit group and the video signal outputted in sync with the pulse signal. Consequently, the power consumption on the clock signal lines can be reduced while the time difference between the clock signal and the video signal can be prevented, thereby making it possible to provide a data signal line driving circuit and an image forming display apparatus which can realize a display of a satisfactory image.

摘要翻译： 一种移位寄存器电路，由多个串行连接的锁存电路组成，用于与时钟信号的上升和下降同步地顺序发送脉冲信号;以及输出电路，用于顺序地将数据信号线同步输出到数据信号线 提供从移位寄存器电路输出的脉冲信号。 移位寄存器电路被分成多个锁存电路组，并且每个锁存电路组中的锁存电路的级数被设定为使从每个锁存电路组输出的脉冲信号和 视频信号与脉冲信号同步输出。 因此，可以减少时钟信号线上的功耗，同时可以防止时钟信号和视频信号之间的时间差，从而可以提供数据信号线驱动电路和可以实现的图像形成显示装置 显示令人满意的图像。

公开(公告)号：US20090207320A1

公开(公告)日：2009-08-20

申请号：US12227491

申请日：2007-03-20

申请人： Shinsaku Shimizu ,  Tamotsu Sakai ,  Ichiro Shiraki

发明人： Shinsaku Shimizu ,  Tamotsu Sakai ,  Ichiro Shiraki

IPC分类号： H04N5/66 ,  G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/3607 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0294 ,  G09G2310/0297

摘要： In one embodiment of the present invention, a display panel drive circuit includes a plurality of circuit blocks each of which includes former circuits and latter circuits. In each of the circuit blocks in the display panel drive circuit, a signal is transmitted from the former circuits to the latter circuits. Further, the display panel drive circuit includes an inter-block shared wire which allows respective two of the circuit blocks adjacent to each other to be connected to each other. Furthermore, in the display panel drive circuit, the signal of the respective two of the circuit blocks adjacent to each other is transmitted in a time division manner, via the inter-block shared wire. This eliminates the need for an external memory or an arithmetic circuit, thereby making it possible to reduce the area of a circuit in a driver.

摘要翻译： 在本发明的一个实施例中，显示面板驱动电路包括多个电路块，每个电路块包括原电路和后一电路。 在显示面板驱动电路的每个电路块中，信号从前一个电路发送到后一个电路。 此外，显示面板驱动电路包括允许彼此相邻的两个电路块彼此连接的块间共享线。 此外，在显示面板驱动电路中，通过块间共享线以时分方式发送彼此相邻的各个电路块的信号。 这消除了对外部存储器或运算电路的需要，从而可以减小驱动器中电路的面积。

公开(公告)号：US08471806B2

公开(公告)日：2013-06-25

申请号：US12227491

申请日：2007-03-20

申请人： Shinsaku Shimizu ,  Tamotsu Sakai ,  Ichiro Shiraki

发明人： Shinsaku Shimizu ,  Tamotsu Sakai ,  Ichiro Shiraki

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3607 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0294 ,  G09G2310/0297

摘要： In one embodiment of the present invention, a display panel drive circuit includes a plurality of circuit blocks each of which includes former circuits and latter circuits. In each of the circuit blocks in the display panel drive circuit, a signal is transmitted from the former circuits to the latter circuits. Further, the display panel drive circuit includes an inter-block shared wire which allows respective two of the circuit blocks adjacent to each other to be connected to each other. Furthermore, in the display panel drive circuit, the signal of the respective two of the circuit blocks adjacent to each other is transmitted in a time division manner, via the inter-block shared wire. This eliminates the need for an external memory or an arithmetic circuit, thereby making it possible to reduce the area of a circuit in a driver.

摘要翻译： 在本发明的一个实施例中，显示面板驱动电路包括多个电路块，每个电路块包括原电路和后一电路。 在显示面板驱动电路的每个电路块中，信号从前一个电路发送到后一个电路。 此外，显示面板驱动电路包括允许彼此相邻的两个电路块彼此连接的块间共享线。 此外，在显示面板驱动电路中，通过块间共享线以时分方式发送彼此相邻的各个电路块的信号。 这消除了对外部存储器或运算电路的需要，从而可以减小驱动器中电路的面积。