公开(公告)号：US07960728B2

公开(公告)日：2011-06-14

申请号：US12499209

申请日：2009-07-08

申请人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Eiji Shibata ,  Kenichi Miyamoto

发明人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Eiji Shibata ,  Kenichi Miyamoto

IPC分类号： H01L23/58 ,  H01L29/76 ,  H01L31/00 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66765

摘要： In a method of manufacturing a TFT substrate in accordance with an exemplary aspect of the present invention, an intrinsic semiconductor film, an impurity semiconductor film, and a conductive film for source lines are formed in succession, and a resist having a thin-film portion and a thick-film portions is formed on the conductive film for source lines. Then, etching is performed by using the resist as a mask, and after that, a part of the conductive film for source lines is exposed by removing the thin-film portion of the resist. Next, the exposed conductive film for source lines is etched by using the thick-film portions of the resist a mask, so that the impurity semiconductor film is exposed. Then, by etching the exposed impurity semiconductor film, a back channel region of a TFT 108 is formed. Further, a dummy back channel region 18a, which is irrelevant to the operation of the finished product, is also formed in a portion other than the TFT 108 region.

摘要翻译： 在根据本发明的示例性方面的制造TFT基板的方法中，依次形成本征半导体膜，杂质半导体膜和源极线用导电膜，并且具有薄膜部分的抗蚀剂 并且在用于源极线的导电膜上形成厚膜部分。 然后，通过使用抗蚀剂作为掩模进行蚀刻，之后，通过去除抗蚀剂的薄膜部分来露出用于源极线的导电膜的一部分。 接下来，通过使用抗蚀剂的掩膜的厚膜部分来蚀刻用于源极线的暴露的导电膜，使得杂质半导体膜暴露。 然后，通过蚀刻暴露的杂质半导体膜，形成TFT 108的背沟道区域。 此外，与TFT 108区域以外的部分也形成与成品的操作无关的虚拟背沟道区域18a。

公开(公告)号：US20100006839A1

公开(公告)日：2010-01-14

申请号：US12499209

申请日：2009-07-08

申请人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Eiji Shibata ,  Kenichi Miyamoto

发明人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Eiji Shibata ,  Kenichi Miyamoto

IPC分类号： H01L23/00 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66765

摘要： In a method of manufacturing a TFT substrate in accordance with an exemplary aspect of the present invention, an intrinsic semiconductor film, an impurity semiconductor film, and a conductive film for source lines are formed in succession, and a resist having a thin-film portion and a thick-film portions is formed on the conductive film for source lines. Then, etching is performed by using the resist as a mask, and after that, a part of the conductive film for source lines is exposed by removing the thin-film portion of the resist. Next, the exposed conductive film for source lines is etched by using the thick-film portions of the resist a mask, so that the impurity semiconductor film is exposed. Then, by etching the exposed impurity semiconductor film, a back channel region of a TFT 108 is formed. Further, a dummy back channel region 18a, which is irrelevant to the operation of the finished product, is also formed in a portion other than the TFT 108 region.

摘要翻译： 在根据本发明的示例性方面的制造TFT基板的方法中，依次形成本征半导体膜，杂质半导体膜和源极线用导电膜，并且具有薄膜部分的抗蚀剂 并且在用于源极线的导电膜上形成厚膜部分。 然后，通过使用抗蚀剂作为掩模进行蚀刻，之后，通过去除抗蚀剂的薄膜部分来露出用于源极线的导电膜的一部分。 接下来，通过使用抗蚀剂的掩膜的厚膜部分来蚀刻用于源极线的暴露的导电膜，使得杂质半导体膜暴露。 然后，通过蚀刻暴露的杂质半导体膜，形成TFT 108的背沟道区域。 此外，与TFT 108区域以外的部分也形成与成品的操作无关的虚拟背沟道区域18a。

公开(公告)号：US07847290B2

公开(公告)日：2010-12-07

申请号：US12411799

申请日：2009-03-26

申请人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Masaru Aoki

发明人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Masaru Aoki

IPC分类号： H01L33/00

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/66765

摘要： In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 μm or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.

摘要翻译： 在使用多色调曝光形成薄膜晶体管时，基线的布线宽度为40μm以下，致密情况下的基布线的布线宽度与相邻布线之间的间隔的比例为1.7，优选 1.0以下。

公开(公告)号：US20090242886A1

公开(公告)日：2009-10-01

申请号：US12411799

申请日：2009-03-26

申请人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Masaru Aoki

发明人： Yasuyoshi Itoh ,  Yuichi Masutani ,  Masaru Aoki

IPC分类号： H01L29/04

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/66765

摘要： In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 μm or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.

摘要翻译： 在使用多色调曝光形成薄膜晶体管时，基线的布线宽度为40μm以下，致密情况下的基布线的布线宽度与相邻布线之间的间隔的比例为1.7，优选 1.0以下。

公开(公告)号：US07826014B2

公开(公告)日：2010-11-02

申请号：US11372086

申请日：2006-03-10

申请人： Shinji Yamashita ,  Yuichi Masutani ,  Shingo Nagano

发明人： Shinji Yamashita ,  Yuichi Masutani ,  Shingo Nagano

IPC分类号： G02F1/1343

CPC分类号： G02F1/133555 ,  G02F1/136213 ,  G02F1/136259

摘要： A semi-transparent TFT array substrate has a TFT including a source electrode, a gate electrode, and a drain electrode. The substrate also has an auxiliary capacitive wiring and a reflective pixel electrode. Further, the substrate has a transparent pixel electrode including an electrode extending from a corner of the rest of the transparent pixel electrode to an edge of the auxiliary capacitive wiring closest to a gate wiring connected to the gate electrode. In addition, the substrate has a source wiring connected to the source electrode. The auxiliary capacitive wiring overlaps a space existing between the reflective pixel electrode and the source wiring. The electrode is disposed between the reflective pixel electrode and the source wiring. A connection which connects the electrode and the rest of the transparent pixel electrode does not overlap the auxiliary capacitive wiring in a plan view. The connection does not overlap the gate wiring.

摘要翻译： 半透明TFT阵列基板具有包括源电极，栅电极和漏电极的TFT。 基板还具有辅助电容布线和反射像素电极。 此外，衬底具有透明像素电极，其包括从透明像素电极的其余部分的角部延伸到最靠近连接到栅电极的栅极布线的辅助电容配线的边缘的电极。 此外，衬底具有连接到源电极的源极布线。 辅助电容布线与存在于反射像素电极和源极布线之间的空间重叠。 电极设置在反射像素电极和源极布线之间。 连接电极和透明像素电极的其余部分的连接在平面图中不与辅助电容布线重叠。 连接不与栅极布线重叠。

公开(公告)号：US07394097B2

公开(公告)日：2008-07-01

申请号：US10973619

申请日：2004-10-27

申请人： Kazuhiro Kobayashi ,  Nobuhiro Nakamura ,  Ken Nakashima ,  Yuichi Masutani

发明人： Kazuhiro Kobayashi ,  Nobuhiro Nakamura ,  Ken Nakashima ,  Yuichi Masutani

IPC分类号： H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136236

摘要： A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The second metallic pattern is surrounded by the semiconductor pattern.

摘要翻译： 一种薄膜晶体管阵列基板，包括绝缘基板，形成在所述绝缘基板上的第一金属图案以及设置在所述第一金属图案上的绝缘膜。 半导体图案设置在绝缘膜上，第二金属图案设置在半导体图案上。 第二金属图案被半导体图案包围。

公开(公告)号：US20060050213A1

公开(公告)日：2006-03-09

申请号：US11219879

申请日：2005-09-07

申请人： Yuichi Masutani ,  Shingo Nagano

发明人： Yuichi Masutani ,  Shingo Nagano

IPC分类号： G02F1/1335

CPC分类号： G02F1/133555 ,  G02F2001/136218

摘要： A transflective liquid crystal display device in which a transmissive area to transmit light to a pixel area and a reflective area as well as a thin film transistor are arranged on an insulating substrate, includes an TFT array substrate having plural gate wirings each provided with a gate electrode and a storage capacitive wiring provided with a storage capacitive electrode made of a first conductive film, plural source wirings each provided with a source electrode and a drain electrode made of a second conductive film, a reflecting pixel electrode extending from the drain electrode, and a transmissive pixel electrode formed through a second insulating film, and an opposite substrate arranged oppositely to the TFT array substrate. The source wirings and the reflecting pixel electrode are arranged apart from each other by a predetermined interval, and a contrast preventing electrode is formed over the interval on the second insulating film.

摘要翻译： 在绝缘基板上配置有向像素区域透射光的透射区域和反射区域以及薄膜晶体管的半透射型液晶显示装置，具有具有多个栅极配线的TFT阵列基板，每个栅极布线均设有栅极 电极和设置有由第一导电膜制成的存储电容电极的存储电容布线，多个源极布线，每个源极配置有由第二导电膜制成的源电极和漏电极，从漏电极延伸的反射像素电极，以及 通过第二绝缘膜形成的透射像素电极和与TFT阵列基板相对布置的相对基板。 源极布线和反射像素电极以预定间隔彼此分开布置，并且在第二绝缘膜上的间隔上形成防反射电极。

公开(公告)号：US5668019A

公开(公告)日：1997-09-16

申请号：US094954

申请日：1993-07-23

申请人： Kazuhiro Kobayashi ,  Hiroyuki Murai ,  Takao Sakamoto ,  Yuichi Masutani

发明人： Kazuhiro Kobayashi ,  Hiroyuki Murai ,  Takao Sakamoto ,  Yuichi Masutani

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L29/66757 ,  H01L29/78621

摘要： An Si thin film (2) for a channel is formed on an insulating substrate (1), and then a gate insulating film (3) made principally of SiO.sub.2 is formed thereon. On the gate insulating film (3) is formed a gate electrode (4) composed of a Si thin film doped with impurities. The gate electrode (4) is patterned by isotropic etching using a photoresist (11) as a mask, and the gate insulating film (3) is patterned by anisotropic etching using the photoresist (11) as a mask into a configuration wider than the gate electrode (4) to be removed from source/drain regions position. The Si thin film (2) is ion implanted with impurities to form source/drain regions of an offset structure. A thin film transistor having an offset or LDD structure and capable of reducing an off-state drain current is fabricated without the need for increased number of masks and for an accurate photolithography technique, such as in alignment accuracy between masks.

摘要翻译： 在绝缘基板（1）上形成用于沟道的Si薄膜（2），然后在其上形成主要由SiO 2制成的栅极绝缘膜（3）。 在栅绝缘膜（3）上形成由掺杂有杂质的Si薄膜构成的栅电极（4）。 通过使用光致抗蚀剂（11）作为掩模的各向同性蚀刻对栅电极（4）进行构图，并且通过使用光致抗蚀剂（11）作为掩模的各向异性蚀刻将栅极绝缘膜（3）图案化成比栅极宽 电极（4）从源/漏区位置移除。 Si薄膜（2）被离子注入杂质以形成偏移结构的源极/漏极区域。 制造具有偏移或LDD结构并且能够降低截止状态漏极电流的薄膜晶体管，而不需要增加数量的掩模和精确的光刻技术，例如掩模之间的对准精度。

公开(公告)号：US07876122B2

公开(公告)日：2011-01-25

申请号：US12411990

申请日：2009-03-26

申请人： Shigeaki Noumi ,  Yuichi Masutani

发明人： Shigeaki Noumi ,  Yuichi Masutani

IPC分类号： G01R31/00

CPC分类号： G02F1/13452 ,  G09G3/006 ,  G09G3/3611 ,  G09G2300/0426

摘要： An array substrate is provided with thereon a display area in which plural pixels are arranged in a matrix shape. Output-side mounting terminals for a source driving circuit chip, which is COG-mounted on a frame area on the outside of the display area, have a plural-row zigzag arrangement. Inspection terminals individually provided in correspondence to the output-side mounting terminals have a zigzag arrangement opposite to the zigzag arrangement of the output-side mounting terminals in a terminal-row direction. Additionally, the output-side mounting terminals and the inspection terminals are disposed below the source driving circuit chip.

摘要翻译： 在阵列基板上设置有以矩阵形状排列有多个像素的显示区域。 用于COG安装在显示区域外侧的框架区域上的源极驱动电路芯片的输出侧安装端子具有多行Z字形布置。 与输出侧安装端子对应地分别设置的检查端子具有与端子排方向上的输出侧安装端子的Z字形排列相对的Z字形排列。 此外，输出侧安装端子和检查端子设置在源极驱动电路芯片的下方。

公开(公告)号：US07470571B2

公开(公告)日：2008-12-30

申请号：US11951832

申请日：2007-12-06

申请人： Nobuaki Ishiga ,  Takuji Yoshida ,  Yuichi Masutani ,  Shingo Nagano

发明人： Nobuaki Ishiga ,  Takuji Yoshida ,  Yuichi Masutani ,  Shingo Nagano

IPC分类号： H01L21/00

CPC分类号： G02F1/136227 ,  G02F1/133555 ,  G02F2001/136236 ,  H01L21/32139 ,  H01L27/124

摘要： A method of producing a thin film transistor array substrate which includes an insulating substrate, a display pixel having a pixel electrode connected to a drain electrode, a gate wiring, and a source wiring perpendicular to the gate wiring, comprising forming a first thin metal multi-layer film an upper layer of which includes aluminum, and spreading a photo-resist, forming the photo-resist to a thickness less in an area connected to a second thin metal film than other area, patterning the first thin metal film, reducing a thickness of the photo-resist layer and removing the photo-resist in the area, removing the upper layer in the area to expose a lower layer, forming an interlayer insulating film and patterning it to expose the lower layer in the area, and patterning the second thin metal film to include the area, to connect the lower layer to the second thin metal film.