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公开(公告)号：US06483495B2
公开(公告)日：2002-11-19
申请号：US09883263
申请日：2001-06-19
IPC分类号： G09G336
CPC分类号： G02F1/13452 , G02F1/13454
摘要： A liquid crystal display device comprises a base substrate including a display region, and a drive circuitry region provided in a surrounding region of the display region, a liquid crystal layer, and a counter substrate facing the base substrate via the liquid crystal layer. A pixel electrode and a pixel driving element for driving the pixel electrode are provided in the display region, a driving circuitry section for controlling the pixel electrode and the pixel driving element is provided in the drive circuitry region. An insulating layer is provided to cover at least one portion of the drive circuitry region. A common transition electrode is provided in the insulating layer. The common transition electrode is electrically connected to a counter electrode provided on the counter substrate.
摘要翻译： 液晶显示装置包括：基板，包括显示区域;以及设置在显示区域的周围区域的驱动电路区域，液晶层，以及经由液晶层面向基板的对置基板。 用于驱动像素电极的像素电极和像素驱动元件设置在显示区域中，用于控制像素电极的驱动电路部分和像素驱动元件设置在驱动电路区域中。 提供绝缘层以覆盖驱动电路区域的至少一部分。 在绝缘层中设置公共的过渡电极。 公共过渡电极与设置在对置基板上的对电极电连接。
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2.发明授权Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行公开(公告)号：US07196699B1
公开(公告)日：2007-03-27
申请号：US09506033
申请日：2000-02-16
IPC分类号： G09G5/00 , G09G3/26 , H03K19/0175 , H03K19/00 , H03K5/153
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。
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公开(公告)号：US07079096B2
公开(公告)日：2006-07-18
申请号：US10253570
申请日：2002-09-24
申请人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
发明人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3614 , G09G3/3688 , G09G2310/0248
摘要： Before a potential of counter electrode is changed, a potential holding circuit fixedly holds potentials of data signal lines S during a non-selective period of scanning signal lines G. This prevents the potentials of the data signal lines S from being an undesirably large potential, which is caused by coupling capacitors between the counter electrode and each data signal line S, whereby it is possible to supply to the pixel capacitor an electric charge corresponding to a gradation to be displayed, by using the relatively low potentials of the data signal lines S. This lowers a power supply voltage of a data signal driving circuit SD, thus reducing the electric power consumption. In short, with this arrangement, a liquid crystal display device can perform an opposed AC drive for line-inversion drive, frame-inversion drive and the like, by low power supply voltage of the data signal line driving circuit SD, thereby reducing the electric power consumption.
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公开(公告)号：US06940500B2
公开(公告)日：2005-09-06
申请号：US10252497
申请日：2002-09-23
申请人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
发明人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
CPC分类号： G09G3/3648 , G09G3/3688 , G09G2310/0248 , G09G2330/021
摘要： A potential of a data signal line S during a scanning period is charged to a substantially intermediate potential of a data signal at a corresponding frame. Thus, extremely large dispersion does not occur in a potential of each pixel capacitor with respect to a potential of the data signal line S, so that it is possible to restrict dispersion of a leak current flowing via an active element of each pixel. Thus, potential variation of a pixel PIX is reduced, so that it is possible to improve display quality during a non-scanning period. That is, in an active-matrix-type liquid crystal display, when a frame frequency is reduced by setting the non-scanning period to be sufficiently larger than a scanning period while a standby image is being displayed so as to realize low power consumption, the display quality is improved.
摘要翻译： 扫描周期期间的数据信号线S的电位被充电到相应帧的数据信号的大致中间电位。 因此，相对于数据信号线S的电位，每个像素电容器的电位不会发生极大的色散，从而可以限制流过每个像素的有源元件的漏电流的色散。 因此，像素PIX的电位变化减小，使得可以在非扫描期间提高显示质量。 也就是说，在有源矩阵型液晶显示器中，当通过在显示待机图像的同时将非扫描周期设置为比扫描周期充分大来降低帧频，从而实现低功耗， 显示质量得到提高。
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5.发明申请Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行公开(公告)号：US20050057556A1
公开(公告)日：2005-03-17
申请号：US10949990
申请日：2004-09-23
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。
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公开(公告)号：US06724361B1
公开(公告)日：2004-04-20
申请号：US09703918
申请日：2000-11-01
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G336
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0289
摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. An output pulse having the same width as the pulse of the clock signal is generated.
摘要翻译： 在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。 时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。 产生具有与时钟信号的脉冲相同宽度的输出脉冲。
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公开(公告)号：US20080036753A1
公开(公告)日：2008-02-14
申请号：US11882533
申请日：2007-08-02
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译： 用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于非显示区域的电压VB或电压VW， 不仅在第一帧中显示，而且在预定数量的帧中显示一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。
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公开(公告)号：US06618043B2
公开(公告)日：2003-09-09
申请号：US09504418
申请日：2000-02-15
IPC分类号： G09G500
CPC分类号： G09G3/3648 , G09G2310/0248 , G09G2330/021
摘要： A precharge circuit is composed of (a) a reference signal input section, to which at least one precharge reference potential is inputted, (b) a control signal input section, to which at least one control signal is inputted, (c) a plurality of signal delay sections for sequentially delaying an output of the control signal input section, and (d) a reference signal switching section for switching, in accordance with outputs of the signal delay sections, between a state of outputting the precharge reference potential of the reference signal input section to each of the data signal lines and a state of non-outputting the same thereto. With this arrangement, the precharge control signal is sequentially delayed within the precharge circuit by the delay circuits composed of inverter circuits or the like, so that timings at which the precharge reference potential is written in the data signal lines are dispersed. By sequentially delaying the control signal within the precharge circuit, reduction of power consumption and excellent image display are realized.
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9.发明授权Latch circuit, shift register circuit and image display device operated with a low consumption of power 有权锁存电路，移位寄存器电路和图像显示设备以低功耗运行公开(公告)号：US06580411B1
公开(公告)日：2003-06-17
申请号：US09300178
申请日：1999-04-27
IPC分类号： G09G336
CPC分类号： H03K3/356121 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2310/0286 , G09G2320/0209 , G09G2320/0257 , G09G2330/021 , H03K3/356139
摘要： If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M15 and M16 are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M12 is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.
摘要翻译： 如果时钟信号ck为“H”，并且（第一控制信号）中的输入脉冲信号为“H”，则n型晶体管M15和M16导通，使输出节点/ OUT具有GND电平。 然后，p型晶体管M12导通，使得输出节点OUT具有Vcc（16V）电平。 因此，当第一和第二控制信号和时钟信号ck处于“H”时，锁存电路LAT作为电平移位器电路工作，并且在任何其它情况下作为电平保持电路工作。 因此，由锁存电路LAT构成的移位寄存器电路用作低电压接口，并且当锁存电路LAT不活动时，时钟信号ck的输入停止，使得时钟的负载和功率的消耗 信号线减少。
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10.发明授权Display device having display area and non-display area, and driving method thereof 有权具有显示区域和非显示区域的显示装置及其驱动方法公开(公告)号：US08130216B2
公开(公告)日：2012-03-06
申请号：US11882533
申请日：2007-08-02
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译： 用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。
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