HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES
    1.
    发明申请
    HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES 有权
    高密度TRENCH MOSFET,具有单面罩预定门和接触孔

    公开(公告)号:US20100291744A1

    公开(公告)日:2010-11-18

    申请号:US12847863

    申请日:2010-07-30

    IPC分类号: H01L21/336

    摘要: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

    摘要翻译: 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。

    High density trench mosfet with single mask pre-defined gate and contact trenches
    2.
    发明授权
    High density trench mosfet with single mask pre-defined gate and contact trenches 有权
    高密度沟槽mosfet与单一掩模预定义的门和接触沟槽

    公开(公告)号:US07879676B2

    公开(公告)日:2011-02-01

    申请号:US12847863

    申请日:2010-07-30

    IPC分类号: H01L21/336

    摘要: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

    摘要翻译: 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。

    HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES
    3.
    发明申请
    HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES 有权
    高密度TRENCH MOSFET,具有单面罩预定门和接触孔

    公开(公告)号:US20100190307A1

    公开(公告)日:2010-07-29

    申请号:US12362414

    申请日:2009-01-29

    IPC分类号: H01L21/336

    摘要: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

    摘要翻译: 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽,并且在栅极沟槽处具有比那些沟槽更宽的开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。

    High density trench MOSFET with single mask pre-defined gate and contact trenches
    4.
    发明授权
    High density trench MOSFET with single mask pre-defined gate and contact trenches 有权
    具有单掩模预定义栅极和接触沟槽的高密度沟槽MOSFET

    公开(公告)号:US07767526B1

    公开(公告)日:2010-08-03

    申请号:US12362414

    申请日:2009-01-29

    IPC分类号: H01L21/336

    摘要: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

    摘要翻译: 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽,并且在栅极沟槽处具有比那些沟槽更宽的开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。

    MANUFACTURING METHODS FOR ACCURATELY ALIGNED AND SELF-BALANCED SUPERJUNCTION DEVICES
    7.
    发明申请
    MANUFACTURING METHODS FOR ACCURATELY ALIGNED AND SELF-BALANCED SUPERJUNCTION DEVICES 审中-公开
    精确对准和自平衡超级设备的制造方法

    公开(公告)号:US20150357406A1

    公开(公告)日:2015-12-10

    申请号:US14298922

    申请日:2014-06-08

    摘要: This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

    摘要翻译: 本发明公开了一种在半导体基板上制造半导体功率器件的方法, 漂移区由外延层组成。 该方法包括:生长第一外延层,然后在外延层顶部形成第一硬掩模层的第一步骤; 第二步骤,施加第一注入掩模以打开多个植入窗口,并施加第二注入掩模以阻挡一些植入窗口,以在第一外延层中相互邻近地注入交替导电类型的多个掺杂区; 以及通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤以形成多个外延层的第三步骤,其中每个外延层被注入交替导电类型的掺杂区域。 然后通过在交变导电类型的掺杂剂区域的顶部上的外延层的顶侧上进行器件制造工艺来进行制造工艺,其具有扩散处理,以将交替导电类型的掺杂区域作为掺杂列合并在 外延层。

    Manufacturing methods for accurately aligned and self-balanced superjunction devices
    8.
    发明授权
    Manufacturing methods for accurately aligned and self-balanced superjunction devices 有权
    精确对准和自平衡超级结装置的制造方法

    公开(公告)号:US08785306B2

    公开(公告)日:2014-07-22

    申请号:US13200683

    申请日:2011-09-27

    IPC分类号: H01L29/06

    摘要: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

    摘要翻译: 一种在半导体基板上制造半导体功率器件的方法,该半导体衬底通过生长第一外延层,然后在外延层的顶部上形成第一硬掩模层,从而支撑由外延层组成的漂移区; 施加第一注入掩模以打开多个植入窗口并且施加第二注入掩模以阻挡所述植入物窗口中的一些以在所述第一外延层中相互邻近地注入交替导电类型的多个掺杂区域; 通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤,以形成多个外延层,然后利用扩散处理在外延层的顶侧上进行器件制造工艺,以将掺杂区域 交替导电类型作为外延层中的掺杂列。