公开(公告)号：US06719874B1

公开(公告)日：2004-04-13

申请号：US09823800

申请日：2001-03-30

申请人： Yehiel Gotkis ,  Aleksander A. Owczarz ,  Miguel A. Saldana ,  David Wei ,  Damon Vincent Williams

发明人： Yehiel Gotkis ,  Aleksander A. Owczarz ,  Miguel A. Saldana ,  David Wei ,  Damon Vincent Williams

IPC分类号： B24B100

CPC分类号： B24B37/32

摘要： A chemical mechanical planarization (CMP) system having a polishing pad, a carrier body for holding a wafer, a retaining ring, and an active retaining ring support is provided. The active retaining ring is defined by a circular ring having a thickness and a width. The circular ring is defined by an elastomeric material. The circular ring is configured to be placed between the retaining ring and the carrier body. The circular ring has a plurality of voids therein, and the plurality of voids are defined in locations around the circular ring. The circular ring has a compressibility level that is set by the elastomeric material and the plurality of voids.

摘要翻译： 提供了具有抛光垫，用于保持晶片的载体主体，保持环和主动挡环支架的化学机械平面化（CMP）系统。 主动保持环由具有厚度和宽度的圆形环限定。 圆环由弹性体材料限定。 圆环被配置成放置在保持环和载体之间。 圆环中具有多个空隙，并且多个空隙限定在圆环周围的位置。 圆环具有由弹性体材料和多个空隙设定的可压缩水平。

公开(公告)号：US20060043596A1

公开(公告)日：2006-03-02

申请号：US11259561

申请日：2005-10-25

申请人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

发明人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

IPC分类号： H01L23/52

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is performed to etch trenches and vias, and filling and planarizing the trenches and vias. The sacrificial layer is etched throughout the plurality of levels of the interconnect metallization structures, thus leaving a voided interconnect metallization structure. The voided interconnect metallization structure is filled with low K dielectric material, thus defining a low K dielectric interconnect metallization structure.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成晶体管结构，并通过沉积牺牲层来形成多层次的互连金属化结构。 执行双镶嵌工艺以蚀刻沟槽和通孔，以及填充和平坦化沟槽和通孔。 牺牲层在互连金属化结构的多个层次上被蚀刻，从而留下空隙的互连金属化结构。 空隙互连金属化结构填充有低K电介质材料，因此限定了低K电介质互连金属化结构。

公开(公告)号：US06656024B1

公开(公告)日：2003-12-02

申请号：US10029742

申请日：2001-12-21

申请人： John M. Boyd ,  David Wei ,  Yehiel Gotkis

发明人： John M. Boyd ,  David Wei ,  Yehiel Gotkis

IPC分类号： B24B500

CPC分类号： B24B37/32 ,  B24B21/04

摘要： A retaining ring is provided. The retaining ring includes a lower annular sleeve having a base. The base has an inner sidewall and an outer sidewall extending therefrom. The lower annular sleeve has at least one hole defined therein. An upper annular sleeve is moveably disposed over the lower annular sleeve. The upper annular sleeve has a top, that has at least one hole defined therein. The top has an inner sidewall and an outer sidewall extending therefrom. A method for reducing a consumption of compressed dry air (CDA) during a chemical mechanical planarization (CMP) operation is also described.

摘要翻译： 提供固定环。 保持环包括具有底座的下环形套筒。 底座具有从其延伸的内侧壁和外侧壁。 下环形套筒具有限定在其中的至少一个孔。 上环形套筒可移动地设置在下环形套筒的上方。 上环形套筒具有顶部，其具有限定在其中的至少一个孔。 顶部具有从其延伸的内侧壁和外侧壁。 还描述了在化学机械平坦化（CMP）操作期间减少压缩干燥空气（CDA）的消耗的方法。

公开(公告)号：US07425501B2

公开(公告)日：2008-09-16

申请号：US11259561

申请日：2005-10-25

申请人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

发明人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is performed to etch trenches and vias, and filling and planarizing the trenches and vias. The sacrificial layer is etched throughout the plurality of levels of the interconnect metallization structures, thus leaving a voided interconnect metallization structure. The voided interconnect metallization structure is filled with low K dielectric material, thus defining a low K dielectric interconnect metallization structure.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成晶体管结构，并通过沉积牺牲层来形成多层次的互连金属化结构。 执行双镶嵌工艺以蚀刻沟槽和通孔，以及填充和平坦化沟槽和通孔。 牺牲层在互连金属化结构的多个层次上被蚀刻，从而留下空隙的互连金属化结构。 空隙互连金属化结构填充有低K电介质材料，因此限定了低K电介质互连金属化结构。

公开(公告)号：US06808442B1

公开(公告)日：2004-10-26

申请号：US10027947

申请日：2001-12-20

申请人： David Wei ,  Yehiel Gotkis ,  Aleksander Owczarz ,  John M. Boyd ,  Rod Kistler

发明人： David Wei ,  Yehiel Gotkis ,  Aleksander Owczarz ,  John M. Boyd ,  Rod Kistler

IPC分类号： B24B100

CPC分类号： B24B37/20 ,  B24B21/20

摘要： An invention is provided for removal rate profile manipulation during a CMP process. An apparatus of the embodiments of the present invention includes an actuator capable of vertical movement perpendicular to a polishing surface of a polishing pad. The actuator is further capable of flexing the polishing pad independently of a pad support device. Also included in the apparatus is an actuator control mechanism that is in communication with the actuator. The actuator control mechanism is capable of controlling an amount of vertical movement of the actuator, allowing the actuator to provide local flexing of the polishing pad to achieve a particular removal rate profile. The actuator can also be capable of horizontal movement parallel to the polishing surface of the polishing pad.

摘要翻译： 提供了一种用于在CMP处理期间的去除速率轮廓操作的发明。 本发明的实施例的装置包括能够垂直于抛光垫的抛光表面垂直运动的致动器。 致动器还能够独立于衬垫支撑装置使抛光垫挠曲。 该装置中还包括与致动器连通的致动器控制机构。 致动器控制机构能够控制致动器的垂直运动量，从而允许致动器提供抛光垫的局部弯曲以实现特定的去除速率曲线。 致动器还能够平行于抛光垫的抛光表面的水平移动。

公开(公告)号：US07875548B2

公开(公告)日：2011-01-25

申请号：US12188145

申请日：2008-08-07

申请人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

发明人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

摘要翻译： 提供了在其上形成有晶体管的衬底上制造半导体结构的方法。 一种方法包括形成多个级别的互连金属化结构。 互连金属化结构的形成包括沉积牺牲层并执行将沟槽，通路和短截线蚀刻到牺牲层中的工艺。 该方法还包括填充和平坦化被蚀刻的沟槽，通路和短截线，然后在互连金属化结构的整个层级上蚀刻除去牺牲层。 蚀刻留下空隙互连金属化结构，其结构上由非电功能的短截线支撑。

公开(公告)号：US20090004845A1

公开(公告)日：2009-01-01

申请号：US12188145

申请日：2008-08-07

申请人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

发明人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

摘要翻译： 提供了在其上形成有晶体管的衬底上制造半导体结构的方法。 一种方法包括形成多个级别的互连金属化结构。 互连金属化结构的形成包括沉积牺牲层并执行将沟槽，通路和短截线蚀刻到牺牲层中的工艺。 该方法还包括填充和平坦化被蚀刻的沟槽，通路和短截线，然后在互连金属化结构的整个层级上蚀刻除去牺牲层。 蚀刻留下空隙互连金属化结构，其结构上由非电功能的短截线支撑。

公开(公告)号：US20050194688A1

公开(公告)日：2005-09-08

申请号：US09821415

申请日：2001-03-28

申请人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

发明人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided. The semiconductor device includes a substrate having transistor devices and a plurality of copper interconnect metallization lines and conductive vias. The plurality of copper interconnect metallization lines and conductive vias are defined in each of a plurality of interconnect levels of the semiconductor device such that the plurality of copper interconnect metallization lines and conductive vias are isolated from each other by an air dielectric. The semiconductor device further includes a plurality of supporting stubs each of which is configured to form a supporting column that extends through the plurality of interconnect levels of the semiconductor device.

摘要翻译： 提供半导体器件。 半导体器件包括具有晶体管器件和多个铜互连金属化线和导电通孔的衬底。 多个铜互连金属化线和导电通孔被限定在半导体器件的多个互连层中的每一个中，使得多个铜互连金属化线和导电通孔通过空气电介质彼此隔离。 半导体器件还包括多个支撑短截线，每个支撑短截线被配置成形成延伸穿过半导体器件的多个互连级别的支撑柱。

公开(公告)号：US06749491B1

公开(公告)日：2004-06-15

申请号：US10033501

申请日：2001-12-26

申请人： Yehiel Gotkis ,  David Wei ,  Aleksander Owzarz

发明人： Yehiel Gotkis ,  David Wei ,  Aleksander Owzarz

IPC分类号： B24B2120

CPC分类号： B24B37/04 ,  B24B21/04 ,  B24B21/20

摘要： An apparatus for reducing non-uniform stretch of a belt used in the CMP system is disclosed. The belt that may be used with the apparatus extends between a first roller and a second roller to define a belt loop with an inner surface and an outer surface to be used for CMP. The apparatus includes a compensating roller that has a first end and a second end where the first end and second end extends a width of the belt. The first end and the second end have a first diameter. The center of the roller has a second diameter that is less than the first diameter. The compensating roller has a symmetrically tapered shape that extends between each of the first end and second end to the center. The compensating roller is positioned inside of the belt loop, and is applied to the inner surface of the belt loop to reduce non-uniform stretch of the belt.

公开(公告)号：US06984892B2

公开(公告)日：2006-01-10

申请号：US09821415

申请日：2001-03-28

申请人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

发明人： Yehiel Gotkis ,  David Wei ,  Rodney Kistler

IPC分类号： H01L23/48 ,  H01L29/00

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided. The semiconductor device includes a substrate having transistor devices and a plurality of copper interconnect metallization lines and conductive vias. The plurality of copper interconnect metallization lines and conductive vias are defined in each of a plurality of interconnect levels of the semiconductor device such that the plurality of copper interconnect metallization lines and conductive vias are isolated from each other by an air dielectric. The semiconductor device further includes a plurality of supporting stubs each of which is configured to form a supporting column that extends through the plurality of interconnect levels of the semiconductor device.

摘要翻译： 提供半导体器件。 半导体器件包括具有晶体管器件和多个铜互连金属化线和导电通孔的衬底。 多个铜互连金属化线和导电通孔被限定在半导体器件的多个互连层中的每一个中，使得多个铜互连金属化线和导电通孔通过空气电介质彼此隔离。 半导体器件还包括多个支撑短截线，每个支撑短截线被配置成形成延伸穿过半导体器件的多个互连级别的支撑柱。