Method for making semiconductor structures implementing sacrificial material
    1.
    发明授权
    Method for making semiconductor structures implementing sacrificial material 有权
    半导体结构实现牺牲材料的方法

    公开(公告)号:US07875548B2

    公开(公告)日:2011-01-25

    申请号:US12188145

    申请日:2008-08-07

    IPC分类号: H01L21/4763

    摘要: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

    摘要翻译: 提供了在其上形成有晶体管的衬底上制造半导体结构的方法。 一种方法包括形成多个级别的互连金属化结构。 互连金属化结构的形成包括沉积牺牲层并执行将沟槽,通路和短截线蚀刻到牺牲层中的工艺。 该方法还包括填充和平坦化被蚀刻的沟槽,通路和短截线,然后在互连金属化结构的整个层级上蚀刻除去牺牲层。 蚀刻留下空隙互连金属化结构,其结构上由非电功能的短截线支撑。

    Method for Making Semiconductor Structures Implementing Sacrificial Material
    2.
    发明申请
    Method for Making Semiconductor Structures Implementing Sacrificial Material 有权
    制造半导体结构实施牺牲材料的方法

    公开(公告)号:US20090004845A1

    公开(公告)日:2009-01-01

    申请号:US12188145

    申请日:2008-08-07

    IPC分类号: H01L21/4763

    摘要: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

    摘要翻译: 提供了在其上形成有晶体管的衬底上制造半导体结构的方法。 一种方法包括形成多个级别的互连金属化结构。 互连金属化结构的形成包括沉积牺牲层并执行将沟槽,通路和短截线蚀刻到牺牲层中的工艺。 该方法还包括填充和平坦化被蚀刻的沟槽,通路和短截线,然后在互连金属化结构的整个层级上蚀刻除去牺牲层。 蚀刻留下空隙互连金属化结构,其结构上由非电功能的短截线支撑。

    METHOD AND APPARATUS FOR REMOVING MATERIAL FROM MICROFEATURE WORKPIECES
    3.
    发明申请
    METHOD AND APPARATUS FOR REMOVING MATERIAL FROM MICROFEATURE WORKPIECES 失效
    从微生物工件中去除材料的方法和装置

    公开(公告)号:US20080064306A1

    公开(公告)日:2008-03-13

    申请号:US11938097

    申请日:2007-11-09

    IPC分类号: B24B55/00

    CPC分类号: B24B37/22 B24B37/24

    摘要: Methods and apparatus for removing materials from microfeature workpieces. One embodiment of a subpad in accordance with the invention comprises a matrix having a first surface configured to support a polishing medium and a second surface opposite the first surface. The subpad in this embodiment further includes a hydro-control agent in the matrix. The hydro-control agent has a hydrophobicity that inhibits liquid from absorbing into the subpad. The hydro-control agent, for example, can be coupling agents that are generally hydrophobic, surfactants that are hydrophobic, or other agents that are compatible with the matrix and at least generally hydrophobic.

    摘要翻译: 从微型工件中去除材料的方法和设备。 根据本发明的子垫的一个实施例包括具有构造成支撑抛光介质的第一表面和与第一表面相对的第二表面的矩阵。 该实施例中的子垫还包括基质中的加氢控制剂。 加氢控制剂具有抑制液体吸收到亚垫中的疏水性。 例如,加氢控制剂可以是通常为疏水性的偶联剂,疏水性表面活性剂或与基质相容并且至少一般疏水的其它试剂。

    Method and apparatus of arrayed, clustered or coupled eddy current sensor configuration for measuring conductive film properties
    4.
    发明授权
    Method and apparatus of arrayed, clustered or coupled eddy current sensor configuration for measuring conductive film properties 失效
    用于测量导电膜性质的阵列,聚集或耦合涡流传感器配置的方法和装置

    公开(公告)号:US07205166B2

    公开(公告)日:2007-04-17

    申请号:US10749531

    申请日:2003-12-30

    IPC分类号: H01L21/66

    摘要: A method for minimizing measuring spot size and noise during film thickness measurement is provided. The method initiates with locating a first eddy current sensor directed toward a first surface associated with a conductive film. The method includes locating a second eddy current sensor directed toward a second surface associated with the conductive film. The first and second eddy current sensors may share a common axis or be offset from each other. The method further includes alternating power supplied to the first eddy current sensor and the second eddy current sensor, such that the first eddy current sensor and the second eddy current sensor are powered one at a time. In one aspect of the invention, a delay time is incorporated between switching power between the first eddy current sensor and the second eddy current sensor. The method also includes calculating the film thickness measurement based on a combination of signals from the first eddy current sensor and the second eddy current sensor. An apparatus and a system are also provided.

    摘要翻译: 提供了一种在膜厚测量期间最小化测量点尺寸和噪声的方法。 该方法通过定位朝向与导电膜相关联的第一表面的第一涡流传感器来启动。 该方法包括定位朝向与导电膜相关联的第二表面的第二涡流传感器。 第一和第二涡流传感器可以共享公共轴线或彼此偏移。 该方法还包括供应给第一涡流传感器和第二涡流传感器的交流电力,使得第一涡流传感器和第二涡流传感器一次一个地供电。 在本发明的一个方面,在第一涡流传感器和第二涡流传感器之间的开关功率之间并入延迟时间。 该方法还包括基于来自第一涡流传感器和第二涡流传感器的信号的组合来计算膜厚度测量。 还提供了一种装置和系统。

    Integration of sensor based metrology into semiconductor processing tools
    5.
    发明授权
    Integration of sensor based metrology into semiconductor processing tools 失效
    将基于传感器的计量学整合到半导体处理工具中

    公开(公告)号:US07128803B2

    公开(公告)日:2006-10-31

    申请号:US10186472

    申请日:2002-06-28

    IPC分类号: C23F1/00 H01L21/306

    摘要: A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A cluster of sensors external to the CMP tool is included. The cluster of sensors is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The cluster of sensors provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.

    摘要翻译: 提供了一种用于处理晶片的系统。 该系统包括化学机械平面化(CMP)工具。 CMP工具包括限定在壳体内的晶片载体。 载体膜固定到底表面并支撑晶片。 嵌入晶片载体的传感器。 传感器被配置为在晶片中感应涡流以确定晶片的接近度和厚度。 包括CMP工具外部的一组传感器。 传感器组与嵌入晶片载体中的传感器进行通信,并且基本上消除了距离灵敏度。 传感器簇提供晶片的初始厚度,以允许对嵌入在晶片载体中的传感器执行校准。 校准偏移了在CMP操作期间确定晶片厚度的不准确性的变量。 还提供了一种方法和装置。

    Method and apparatus for slope to threshold conversion for process state monitoring and endpoint detection
    6.
    发明授权
    Method and apparatus for slope to threshold conversion for process state monitoring and endpoint detection 有权
    用于过程状态监测和端点检测的斜率到阈值转换的方法和装置

    公开(公告)号:US07010468B2

    公开(公告)日:2006-03-07

    申请号:US11030374

    申请日:2005-01-05

    IPC分类号: H04B15/00

    CPC分类号: G05B23/0254 H01L22/26

    摘要: A method for converting a slope based detection task to a threshold based detection task is provided. The method initiates with defining an approximation equation for a set of points corresponding to values of a process being monitored. Then, an expected value at a current point of the process being monitored is predicted. Next, a difference between a measured value at the current point of the process being monitored and the corresponding expected value is calculated. Then, the difference is monitored for successive points to detect a deviation value between the measured value and the expected value. Next, a transition point for the process being monitored is identified based on the detection of the deviation value. A processing system configured to provide real time data for a slope based transition and a computer readable media are also provided.

    摘要翻译: 提供了一种将基于斜率的检测任务转换为基于阈值的检测任务的方法。 该方法通过为对应于被监视的进程的值的一组点定义近似方程来启动。 然后,预测在被监视的处理的当前点的期望值。 接下来,计算被监视处理的当前点的测量值与对应的期望值之间的差。 然后,对连续点监测差异,以检测测量值和预期值之间的偏差值。 接下来,基于偏差值的检测来识别被监视处理的转变点。 还提供了一种处理系统,其被配置为提供用于基于斜率的转换的实时数据和计算机可读介质。

    SEMICONDUCTOR STRUCTURE IMPLEMENTING LOW-K DIELECTRIC MATERIALS AND SUPPORTING STUBS
    7.
    发明申请
    SEMICONDUCTOR STRUCTURE IMPLEMENTING LOW-K DIELECTRIC MATERIALS AND SUPPORTING STUBS 有权
    半导体结构实现低K电介质材料和支撑材料

    公开(公告)号:US20050194688A1

    公开(公告)日:2005-09-08

    申请号:US09821415

    申请日:2001-03-28

    摘要: A semiconductor device is provided. The semiconductor device includes a substrate having transistor devices and a plurality of copper interconnect metallization lines and conductive vias. The plurality of copper interconnect metallization lines and conductive vias are defined in each of a plurality of interconnect levels of the semiconductor device such that the plurality of copper interconnect metallization lines and conductive vias are isolated from each other by an air dielectric. The semiconductor device further includes a plurality of supporting stubs each of which is configured to form a supporting column that extends through the plurality of interconnect levels of the semiconductor device.

    摘要翻译: 提供半导体器件。 半导体器件包括具有晶体管器件和多个铜互连金属化线和导电通孔的衬底。 多个铜互连金属化线和导电通孔被限定在半导体器件的多个互连层中的每一个中,使得多个铜互连金属化线和导电通孔通过空气电介质彼此隔离。 半导体器件还包括多个支撑短截线,每个支撑短截线被配置成形成延伸穿过半导体器件的多个互连级别的支撑柱。

    Integration of sensor based metrology into semiconductor processing tools
    9.
    发明申请
    Integration of sensor based metrology into semiconductor processing tools 失效
    将传感器计量学整合到半导体加工工具中

    公开(公告)号:US20050072528A1

    公开(公告)日:2005-04-07

    申请号:US10186472

    申请日:2002-06-28

    摘要: A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded in the wafer carrier. The sensor is configured to induce an eddy current in the wafer to determine a proximity and a thickness of the wafer. A cluster of sensors external to the CMP tool is included. The cluster of sensors is in communication with the sensor embedded in the wafer carrier and substantially eliminates a distance sensitivity. The cluster of sensors provides an initial thickness of the wafer to allow for a calibration to be performed on the sensor embedded in the wafer carrier. The calibration offsets variables causing inaccuracies in the determination of the thickness of the wafer during CMP operation. A method and an apparatus are also provided.

    摘要翻译: 提供了一种用于处理晶片的系统。 该系统包括化学机械平面化(CMP)工具。 CMP工具包括限定在壳体内的晶片载体。 载体膜固定到底表面并支撑晶片。 嵌入晶片载体的传感器。 传感器被配置为在晶片中感应涡流以确定晶片的接近度和厚度。 包括CMP工具外部的一组传感器。 传感器组与嵌入晶片载体中的传感器进行通信,并且基本上消除了距离灵敏度。 传感器簇提供晶片的初始厚度,以允许对嵌入在晶片载体中的传感器执行校准。 校准偏移了在CMP操作期间确定晶片厚度的不准确性的变量。 还提供了一种方法和装置。