公开(公告)号：US07716542B2

公开(公告)日：2010-05-11

申请号：US11939282

申请日：2007-11-13

Applicant: Yeong-Jar Chang ,  Chung-Fu Lin

Inventor： Yeong-Jar Chang ,  Chung-Fu Lin

IPC: G01R31/28 ,  G11C29/00 ,  G06F11/00

CPC classification number: G11C29/16 ,  G01R31/318552 ,  G06F11/2215 ,  G11C29/12015 ,  G11C29/14

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract translation: 提供了可编程存储器内置自检电路及其时钟切换电路。 存储器内置的自检电路能够提供用户预设的更多的自检功能，简化了现有技术中的冗余电路，并借助于指令解码器和内置功能降低了芯片面积并降低了成本 自检控制器。 本发明还提供了一些存储器的外围控制电路。 控制电路占用的面积较小，能够更灵活地测试存储器。 本发明还提供一种能够在不同时钟速度下正确测试芯片的时钟切换电路，这有利于提高嵌入在芯片中的存储器的可测试性和可分析性，从而增加故障覆盖。

公开(公告)号：US20090125763A1

公开(公告)日：2009-05-14

申请号：US11939282

申请日：2007-11-13

Applicant: Yeong-Jar Chang ,  Chung-Fu Lin

Inventor： Yeong-Jar Chang ,  Chung-Fu Lin

IPC: G11C29/08 ,  G06F11/26

CPC classification number: G11C29/16 ,  G01R31/318552 ,  G06F11/2215 ,  G11C29/12015 ,  G11C29/14

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract translation: 提供了可编程存储器内置自检电路及其时钟切换电路。 存储器内置的自检电路能够提供用户预设的更多自检功能，简化了现有技术中的冗余电路，并通过指令解码器和内置的降低芯片面积和降低成本 自检控制器。 本发明还提供了一些存储器的外围控制电路。 控制电路占用的面积较小，能够更灵活地测试存储器。 本发明还提供一种能够在不同时钟速度下正确测试芯片的时钟切换电路，这有利于提高嵌入在芯片中的存储器的可测试性和可分析性，从而增加故障覆盖。

公开(公告)号：US20100257415A1

公开(公告)日：2010-10-07

申请号：US12416646

申请日：2009-04-01

Applicant: Chung-Fu Lin ,  Yeong-Jar Chang

Inventor： Chung-Fu Lin ,  Yeong-Jar Chang

IPC: G11C29/12 ,  G06F11/22 ,  G06F12/02

CPC classification number: G11C29/16 ,  G11C29/20 ,  G11C2029/0401

Abstract: An instruction-based programmable memory built-in self test (P-MBIST) circuit and an address generator thereof are provided. The P-MBIST circuit generates control signals according to the decoding of compact test instructions provided by an external automatic test equipment (ATE). The address generator generates memory addresses according to the control signals. The control signals and the memory addresses are sent to an embedded memory to perform the MBIST. The algorithm-specific design of the P-MBIST circuit and the address generator enables them to support multiple test algorithms at full clock speed and occupy smaller chip area.

Abstract translation: 提供了基于指令的可编程存储器内置自测（P-MBIST）电路及其地址发生器。 P-MBIST电路根据由外部自动测试设备（ATE）提供的紧凑测试指令的解码产生控制信号。 地址生成器根据控制信号产生存储器地址。 控制信号和存储器地址被发送到嵌入式存储器以执行MBIST。 P-MBIST电路和地址发生器的算法特定设计使得它们能够以全时钟速度支持多种测试算法，并占用更小的芯片面积。

公开(公告)号：US20090110102A1

公开(公告)日：2009-04-30

申请号：US12345481

申请日：2008-12-29

Applicant: Ghia-Ming Hong ,  Chia-Wei Chang ,  Yan-Hua Peng ,  Kuang-Chih Liu ,  Chung-Fu Lin

Inventor： Ghia-Ming Hong ,  Chia-Wei Chang ,  Yan-Hua Peng ,  Kuang-Chih Liu ,  Chung-Fu Lin

IPC: H04L27/28 ,  H04L7/00

CPC classification number: H03M1/0665 ,  H03M1/804 ,  H03M3/502 ,  H03M7/165 ,  H03M7/3026

Abstract: A signal routing method adapted to a DWA structure is provided. The signal routing method at least includes following steps. An M-bit input digital signal is provided. The odd bit in the input digital signal is routed into a low-bit signal of an output digital signal, and the even bit in the input digital signal is routed into a high-bit signal of the output digital signal, wherein the output digital signal has M bits.

Abstract translation: 提供了适用于DWA结构的信号路由方法。 信号路由方法至少包括以下步骤。 提供M位输入数字信号。 输入数字信号中的奇数位被路由到输出数字信号的低位信号，并且输入数字信号中的偶数位被路由到输出数字信号的高位信号，其中输出数字信号 有M位。

公开(公告)号：US20090040086A1

公开(公告)日：2009-02-12

申请号：US11835094

申请日：2007-08-07

Applicant: Ghia-Ming Hong ,  Chia-Wei Chang ,  Yan-Hua Peng ,  Kuang-Chih Liu ,  Chung-Fu Lin

Inventor： Ghia-Ming Hong ,  Chia-Wei Chang ,  Yan-Hua Peng ,  Kuang-Chih Liu ,  Chung-Fu Lin

IPC: H03M1/66

CPC classification number: H03M1/0665 ,  H03M1/804 ,  H03M3/502 ,  H03M7/165 ,  H03M7/3026

Abstract: A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.

Abstract translation: 提供了包括第一延迟单元，二进制到温度计代码转换器，加法器，第二延迟单元，解码器，桶形移位器和多个信号线的数据加权平均（DWA）结构。 第一延迟单元延迟输入数字信号。 二进制到温度计代码转换器将第一延迟单元的输出信号转换成热代码。 第二延迟单元延迟加法器的输出信号。 加法器将输入数字信号加到第二延迟单元的输出信号上。 解码器解码第二延迟单元的输出信号。 桶形移位器根据解码器的输出信号从热代码生成输出信号。 信号线将桶形移位器的输出信号路由到两个独立的控制信号组。

公开(公告)号：US07486210B1

公开(公告)日：2009-02-03

申请号：US11835094

申请日：2007-08-07

Applicant: Ghia-Ming Hong ,  Chia-Wei Chang ,  Yan-Hua Peng ,  Kuang-Chih Liu ,  Chung-Fu Lin

Inventor： Ghia-Ming Hong ,  Chia-Wei Chang ,  Yan-Hua Peng ,  Kuang-Chih Liu ,  Chung-Fu Lin

IPC: H03M7/00

CPC classification number: H03M1/0665 ,  H03M1/804 ,  H03M3/502 ,  H03M7/165 ,  H03M7/3026

Abstract: A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.

Abstract translation: 提供了包括第一延迟单元，二进制到温度计代码转换器，加法器，第二延迟单元，解码器，桶形移位器和多个信号线的数据加权平均（DWA）结构。 第一延迟单元延迟输入数字信号。 二进制到温度计代码转换器将第一延迟单元的输出信号转换成热代码。 第二延迟单元延迟加法器的输出信号。 加法器将输入数字信号加到第二延迟单元的输出信号上。 解码器解码第二延迟单元的输出信号。 桶形移位器根据解码器的输出信号从热代码生成输出信号。 信号线将桶形移位器的输出信号路由到两个独立的控制信号组。