公开(公告)号：US20050008238A1

公开(公告)日：2005-01-13

申请号：US10910027

申请日：2004-08-03

申请人： Yi-Jen Chiu ,  Rajesh Hingorani ,  Obed Duardo ,  Paul Wilford

发明人： Yi-Jen Chiu ,  Rajesh Hingorani ,  Obed Duardo ,  Paul Wilford

IPC分类号： H03M7/42 ,  H04N7/26 ,  G06K9/36 ,  G06K9/46

CPC分类号： H03M7/42 ,  H04N19/91

摘要： A method is disclosed for decoding multiple-coded symbols from a coded input symbol stream in a single clock cycle. The method constructs an original Huffman look-up table by extending the associated Huffman tree to decode multiple symbols in one clock cycle in a first embodiment and decodes multiple DCT coefficient symbols in an alternate embodiment. An advantage of the method is that the depth of the new Huffman tree is adjustable thereby making the method easily adaptable to various hardware architectures. A further advantage of the present invention is that the decoding process speed is significantly increased while the size of the lookup table is nominally increased.

摘要翻译： 公开了一种用于在单个时钟周期中从编码输入符号流解码多重编码符号的方法。 该方法通过在第一实施例中在一个时钟周期内扩展相关联的霍夫曼树来解码多个符号来构造原始霍夫曼查找表，并且在替代实施例中解码多个DCT系数符号。 该方法的一个优点是新的霍夫曼树的深度是可调的，从而使该方法容易适应各种硬件架构。 本发明的另一个优点是，在查询表的大小名义上增加时，解码处理速度显着增加。

公开(公告)号：US07043088B2

公开(公告)日：2006-05-09

申请号：US10910027

申请日：2004-08-03

申请人： Yi-Jen Chiu ,  Rajesh Hingorani ,  Obed Duardo ,  Paul Albin Wilford

发明人： Yi-Jen Chiu ,  Rajesh Hingorani ,  Obed Duardo ,  Paul Albin Wilford

IPC分类号： G06K9/36

CPC分类号： H03M7/42 ,  H04N19/91

摘要： A method is disclosed for decoding multiple-coded symbols from a coded input symbol stream in a single clock cycle. The method constructs an original Huffman look-up table by extending the associated Huffman tree to decode multiple symbols in one clock cycle in a first embodiment and decodes multiple DCT coefficient symbols in an alternate embodiment. An advantage of the method is that the depth of the new Huffman tree is adjustable thereby making the method easily adaptable to various hardware architectures. A further advantage of the present invention is that the decoding process speed is significantly increased while the size of the lookup table is nominally increased.

摘要翻译： 公开了一种用于在单个时钟周期中从编码输入符号流解码多重编码符号的方法。 该方法通过在第一实施例中在一个时钟周期内扩展相关联的霍夫曼树来解码多个符号来构造原始霍夫曼查找表，并且在替代实施例中解码多个DCT系数符号。 该方法的一个优点是新的霍夫曼树的深度是可调的，从而使该方法容易适应各种硬件架构。 本发明的另一个优点是，在查询表的大小名义上增加时，解码处理速度显着增加。

公开(公告)号：US06771824B1

公开(公告)日：2004-08-03

申请号：US09473809

申请日：1999-12-28

申请人： Yi-Jen Chiu ,  Rajesh Hingorani ,  Obed Duardo ,  Paul Albin Wilford

发明人： Yi-Jen Chiu ,  Rajesh Hingorani ,  Obed Duardo ,  Paul Albin Wilford

IPC分类号： G06K936

CPC分类号： H03M7/42 ,  H04N19/91

摘要： A method is disclosed for decoding multiple-coded symbols from a coded input symbol stream in a single clock cycle. The method constructs an original Huffman look-up table by extending the associated Huffman tree to decode multiple symbols in one clock cycle in a first embodiment and decodes multiple DCT coefficient symbols in an alternate embodiment. An advantage of the method is that the depth of the new Huffman tree is adjustable thereby making the method easily adaptable to various hardware architectures. A further advantage of the present invention is that the decoding process speed is significantly increased while the size of the look-up table is nominally increased.

摘要翻译： 公开了一种用于在单个时钟周期中从编码输入符号流解码多重编码符号的方法。 该方法通过在第一实施例中在一个时钟周期内扩展相关联的霍夫曼树来解码多个符号来构造原始霍夫曼查找表，并且在替代实施例中解码多个DCT系数符号。 该方法的一个优点是新的霍夫曼树的深度是可调的，从而使该方法容易适应各种硬件架构。 本发明的另一个优点是，在查询表的大小名义上增加时，解码处理速度显着增加。

公开(公告)号：US06940768B2

公开(公告)日：2005-09-06

申请号：US10699932

申请日：2003-11-04

申请人： James A. Dahlberg ,  Obed Duardo

发明人： James A. Dahlberg ,  Obed Duardo

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/1093 ,  G11C7/222

摘要： A double data rate (DDR) synchronous dynamic RAM (SDRAM), or DDR-SDRAM, memory controller employing a delay locked loop (DLL) circuit to delay an SDRAM data strobe (DQS) signal to the center, or ‘eye’ of the read data window. However, in distinction from conventional techniques, the initial delay determined by the DLL is fine tuned with an offset determined by a memory test. Moreover, in an additional embodiment, the delay may be further adjusted during operation to compensate for environmental conditions by a PVT (process, value, temperature) circuit.

摘要翻译： 使用延迟锁定环（DLL）电路将SDRAM数据选通（DQS）信号延迟到中心的双倍数据速率（DDR）同步动态RAM（SDRAM）或DDR-SDRAM存储器控制器，或者“ 读取数据窗口。 然而，与常规技术不同，由DLL确定的初始延迟通过由存储器测试确定的偏移进行微调。 此外，在另外的实施例中，可以在操作期间进一步调整延迟以通过PVT（过程，值，温度）电路补偿环境条件。

公开(公告)号：US06819157B2

公开(公告)日：2004-11-16

申请号：US09991231

申请日：2001-11-15

申请人： Xianguo Cao ,  Obed Duardo ,  Bo Ye

发明人： Xianguo Cao ,  Obed Duardo ,  Bo Ye

IPC分类号： H03H1126

CPC分类号： G06F1/10 ,  H03L7/0814

摘要： A delay compensation circuit that determines the effects of process, voltage, and temperature (PVT) conditions of a chip by measuring the effective delay time of delay components inside the chip. The delay compensation circuit includes a plurality of sampler modules, each of which receives a delayed clock signal from one of a series of delay cells within a tapped delay circuit. The delay compensation circuit generates an output value based on the total number of sampling modules that lock into a fixed input signal using the delayed clock signals. Since the delay time of each delay cell changes based on variations of PVT conditions, the output values generated by the delay compensation circuit are determinate of PVT conditions in the chip. These output values can be used to design components to compensate for variances in PVT conditions or to control a variable delay component based on detected PVT conditions.

摘要翻译： 一种延迟补偿电路，通过测量芯片内的延迟元件的有效延迟时间来确定芯片的工艺，电压和温度（PVT）条件的影响。 延迟补偿电路包括多个采样器模块，每个采样器模块从抽头延迟电路中的一系列延迟单元中的一个接收延迟的时钟信号。 延迟补偿电路使用延迟的时钟信号，基于锁定到固定输入信号的采样模块的总数来产生输出值。 由于每个延迟单元的延迟时间根据PVT条件的变化而变化，所以由延迟补偿电路产生的输出值确定了芯片中的PVT条件。 这些输出值可用于设计组件以补偿PVT条件中的方差，或者根据检测到的PVT条件来控制可变延迟分量。

公开(公告)号：US20050105349A1

公开(公告)日：2005-05-19

申请号：US10699932

申请日：2003-11-04

申请人： James Dahlberg ,  Obed Duardo

发明人： James Dahlberg ,  Obed Duardo

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/1093 ,  G11C7/222

摘要： A double data rate (DDR) synchronous dynamic RAM (SDRAM), or DDR-SDRAM, memory controller employing a delay locked loop (DLL) circuit to delay an SDRAM data strobe (DQS) signal to the center, or ‘eye’ of the read data window. However, in distinction from conventional techniques, the initial delay determined by the DLL is fine tuned with an offset determined by a memory test. Moreover, in an additional embodiment, the delay may be further adjusted during operation to compensate for environmental conditions by a PVT (process, value, temperature) circuit.