公开(公告)号：US06529045B2

公开(公告)日：2003-03-04

申请号：US09406938

申请日：1999-09-28

申请人： Yibin Ye ,  Reed D. Spotten ,  Vivek K. De

发明人： Yibin Ye ,  Reed D. Spotten ,  Vivek K. De

IPC分类号： H03K19096

CPC分类号： H03K19/0963 ,  H03K19/01728

摘要： A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, with the gate of the clock transistor coupled to receive an inverse clock signal. A first inverter and a second inverter are connected in series such that the input of the first inverter is connected to the output of the second inverter. The input of the second inverter is connected to the dynamic output node. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection.

摘要翻译： 提供多米诺骨牌逻辑电路。 电路包括耦合在动态输出节点和高电压连接之间的n沟道时钟晶体管，时钟晶体管的栅极被耦合以接收反时钟信号。 第一反相器和第二反相器串联连接，使得第一反相器的输入连接到第二反相器的输出。 第二反相器的输入连接到动态输出节点。 N沟道电平保持器晶体管连接在动态输出节点和高压连接之间，电平保持晶体管的栅极连接到第一个反相器的输出端。 下拉电路连接在动态输出节点和低压连接之间。

公开(公告)号：US07403426B2

公开(公告)日：2008-07-22

申请号：US11137905

申请日：2005-05-25

申请人： Fatih Hamzaoglu ,  Kevin Zhang ,  Nam Sung Kim ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  Bo Zheng

发明人： Fatih Hamzaoglu ,  Kevin Zhang ,  Nam Sung Kim ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  Bo Zheng

IPC分类号： G11C11/34

CPC分类号： G11C5/14 ,  G11C11/413

摘要： In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

摘要翻译： 在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。 可以公开和/或要求保护其他实施例。

公开(公告)号：US07385865B2

公开(公告)日：2008-06-10

申请号：US11001870

申请日：2004-12-01

申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Gunjan H. Pandya ,  Vivek K. De

发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Gunjan H. Pandya ,  Vivek K. De

IPC分类号： G11C7/00 ,  G11C11/00

CPC分类号： G11C11/419

摘要： In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.

摘要翻译： 在一个实施例中，提供了包括一个或多个列的存储器阵列，每个列包括被分成位单元组的多个位单元，每组比特单元可控制地耦合到单独的位线。

公开(公告)号：US07355246B2

公开(公告)日：2008-04-08

申请号：US11268430

申请日：2005-11-07

申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： H01L29/76

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

公开(公告)号：US07321502B2

公开(公告)日：2008-01-22

申请号：US10956285

申请日：2004-09-30

申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Alavi Mohsen ,  Vivek K. De

发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Alavi Mohsen ,  Vivek K. De

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.

摘要翻译： 描述了一种在驱动电流通过电容器的同时在电容器的电介质材料内感应电介质击穿的方法。 电流特定于正在写入电容器的数据。 该方法还涉及通过解释由电容器电阻确定的电容器的行为来读取数据，其中电容器的电阻是诱导和驱动的结果。

公开(公告)号：US06992339B2

公开(公告)日：2006-01-31

申请号：US10750572

申请日：2003-12-31

申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： H01L27/10

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

公开(公告)号：US06906973B1

公开(公告)日：2005-06-14

申请号：US10746148

申请日：2003-12-24

申请人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C7/00 ,  G11C7/12

CPC分类号： G11C7/12

摘要： Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.

摘要翻译： 一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电， 使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。 此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

公开(公告)号：US06831871B2

公开(公告)日：2004-12-14

申请号：US10334456

申请日：2002-12-30

申请人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De

发明人： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C2207/2281

摘要： According to some embodiments, provided are a memory cell, a bit-line coupled to the memory cell, a pre-charge circuit coupled to the bit-line to pre-charge the bit-line, and a discharge device coupled to the bit-line to discharge the bit-line prior to a read of the memory cell.

公开(公告)号：US06683467B1

公开(公告)日：2004-01-27

申请号：US09672689

申请日：2000-09-29

申请人： Ali Keshavarzi ,  David M. Wu ,  Yibin Ye ,  Vivek K. De

发明人： Ali Keshavarzi ,  David M. Wu ,  Yibin Ye ,  Vivek K. De

IPC分类号： G01R3102

CPC分类号： G01R31/2817

摘要： A method and device are provided for stress testing a chip. The chip may be partitioned into at least a first block and a second block. Burn-in stress testing may be performed on electronic devices within the first block without simultaneously performing burn-in stress testing on electronic devices within the second block. A burn-in stress testing device may perform the burn-in testing. A control device may be coupled to the burn-in stress testing device to enable burn-in stress testing on electronic devices within at least the first block of the chip without simultaneously enabling burn-in stress testing on the second block of the chip.

摘要翻译： 提供了一种用于芯片压力测试的方法和装置。 芯片可以被划分成至少第一块和第二块。 老化压力测试可以在第一块内的电子设备上执行，而不对第二块内的电子设备进行同时进行老化压力测试。 老化压力测试装置可执行老化测试。 控制装置可以耦合到老化压力测试装置，以在芯片的至少第一块内的电子装置上实现耐久性测试，而不必在芯片的第二块上同时进行老化压力测试。

公开(公告)号：US06169419A

公开(公告)日：2001-01-02

申请号：US09151177

申请日：1998-09-10

申请人： Vivek K. De ,  Yibin Ye

发明人： Vivek K. De ,  Yibin Ye

IPC分类号： H03K190948

CPC分类号： H03K19/0016

摘要： Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.

摘要翻译： 使用晶体管堆叠效应减少内部电路块中的备用漏电流。 对于一个实施例，一种装置包括要耦合到包括多个逻辑门的电路块的备用泄漏减小电路。 备用泄漏降低电路在电路块的待机模式期间在多个逻辑门中的每一个处引起堆叠效应，通过关闭两个或更多个相同类型（n型或p型）的串联耦合晶体管 每个逻辑门。