公开(公告)号：US4896271A

公开(公告)日：1990-01-23

申请号：US144829

申请日：1988-01-14

申请人： Yih-Chyun Jenq ,  Philip S. Crosby

发明人： Yih-Chyun Jenq ,  Philip S. Crosby

IPC分类号： G01R13/20 ,  G01R29/00 ,  G01R29/02 ,  G01R31/317 ,  G01R31/3177

CPC分类号： G01R31/31709 ,  G01R29/00 ,  G01R31/3177

摘要： Jitter in a clock signal is measured by using the clock signal to clock a digitizer repetitively digitizing a highly stable sine wave signal so as to produce a first data sequence representing the magnitiude of the sine wave signal as a function of time. This first data sequence is normalized to produce a second data sequence having data elements that vary between maximum and minimun magnitudes of +1 and -1. The arcsine of each element of the second data sequence is then determined to provide a monotonically increasing third data sequence, wherein each element of the third data sequence indicates a phase angle associated with a corresponding element of the second data sequence. A fourth data sequence is then generated, each element of the fourth data sequence representing a difference between a phase angle represented by a corresponding element of the third data sequence and a phase angle that the corresponding element of the third data sequence would represent if the clock signal had a constant frequency. The fourth data sequence provides a measure of clock signal jitter as a function of time.

摘要翻译： 通过使用时钟信号来测量时钟信号中的抖动，以对数字转换器进行时钟反复数字化高稳定正弦波信号，以产生表示作为时间的函数的正弦波信号的幅度的第一数据序列。 该第一数据序列被归一化以产生具有在+1和-1的最大值和最小值之间变化的数据元素的第二数据序列。 然后确定第二数据序列的每个元素的反正弦，以提供单调递增的第三数据序列，其中第三数据序列的每个元素指示与第二数据序列的相应元素相关联的相位角。 然后生成第四数据序列，第四数据序列的每个元素表示由第三数据序列的对应元素表示的相位角与第三数据序列的相应元素如果时钟 信号具有恒定的频率。 第四个数据序列提供时钟信号抖动的测量作为时间的函数。

公开(公告)号：US4858142A

公开(公告)日：1989-08-15

申请号：US81943

申请日：1987-08-05

申请人： Yih-Chyun Jenq ,  Philip S. Crosby

发明人： Yih-Chyun Jenq ,  Philip S. Crosby

IPC分类号： H03M1/10 ,  G01R31/3177 ,  H03M1/00

CPC分类号： G01R31/3177 ,  H03M1/1071

摘要： A method and apparatus for determining the effective bits of resolution of a digitizer wherein amplitude, frequency, phase angle and offset parameters characterizing a sinewave input signal to the digitizer are estimated from the waveform data sequence produced by the digitizer in response to the input signal. These estimated parameters are used to develop a model of the sinewave signal, and the effective bits of resolution of the digitizer are then determined by the comparing measured magnitudes of the sinewave signal as represented by the waveform data sequence to estimated magnitudes of the input signal being determined from the model.

公开(公告)号：US5426738A

公开(公告)日：1995-06-20

申请号：US171752

申请日：1993-12-21

申请人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng

发明人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng

IPC分类号： H03K19/173 ,  H05K1/00 ,  G06F3/00

CPC分类号： H03K19/1736 ,  H05K1/0286

摘要： A field programmable circuit board provides a set of sockets for receiving electronic components, a set of connector pins for providing external access to the board and an array of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports automatically sense direction of flow of bidirectional signals routed by the FPIDs and buffer the signals in the appropriate direction. Each FPID buffer also samples and stores data indicating states of the buffered signals over several system clock cycles for subsequent read out by the host computer.

摘要翻译： 现场可编程电路板提供一组用于接收电子元件的插座，一组连接器引脚，用于提供对板的外部访问以及现场可编程互连器件（FPID）阵列。 FPID是缓冲的，多端口交叉点开关，其可以由主机计算机来选择性地将安装在插座中的部件的端子彼此连接或连接到外部连接器引脚。 FPID端口内的信号缓冲区会自动检测由FPID路由的双向信号的流向，并按适当的方向缓冲信号。 每个FPID缓冲器还在几个系统时钟周期上采样和存储指示缓冲信号状态的数据，以供主计算机随后读出。

公开(公告)号：US4800443A

公开(公告)日：1989-01-24

申请号：US85425

申请日：1987-08-14

申请人： Regis J. Crinon ,  Yih-Chyun Jenq

发明人： Regis J. Crinon ,  Yih-Chyun Jenq

IPC分类号： B41J2/52 ,  G06K15/00 ,  G06T5/00 ,  H04N1/405 ,  H04N1/40

CPC分类号： H04N1/4051

摘要： A two-dimensional array of binary values is used to control operation of a bi-level imaging device. The array of binary values is formed by applying an enhanced array g(u,v) to a two-dimensional array of threshold values. A two-dimensional array of pixel value f(u,v) is used to form the enhanced array g(u,v) such that g(u,v)=m.sub.f +k[f(u,v)-m.sub.f ] where m.sub.f is the average value of f(u+a, v+b) from a=-L to a=+L and b=-M to b=+M and k is a gain function which depends on the standard deviation in f(u+c, v+d) from c=-N to c=+N and d=-P to d=+P. L, M, N and P define the sub-array over which the standard deviation is calculated. Preferably, L, M, N and P are each equal to 2. The value of k is a decreasing function of the standard deviation: the larger the standard deviation, the smaller the gain factor k. The rate at which k decreases with increase in the standard deviation depends on the edge sampling characteristics of the array of threshold values.

公开(公告)号：US5202593A

公开(公告)日：1993-04-13

申请号：US785299

申请日：1991-10-30

申请人： Thomas B. Huang ,  Yih-Chyun Jenq ,  Keith Lofstrom

发明人： Thomas B. Huang ,  Yih-Chyun Jenq ,  Keith Lofstrom

IPC分类号： H03K19/0175 ,  H03K5/02 ,  H04L5/16

CPC分类号： H03K5/026

摘要： A bi-directional bus repeater includes two unidirectional bus repeaters connected for retransmitting signals in opposite directions between two buses. When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.

摘要翻译： 双向总线中继器包括两个单向总线中继器，用于在两条总线之间的相反方向重新发送信号。 当外部总线驱动器将总线拉低时，其中一个单向总线中继器将另一个总线拉低。 当外部总线驱动器允许总线上升到高逻辑电平时，单向总线中继器临时向另一个总线提供高充电电流，以快速将其拉高。 每个单向总线中继器还产生指示何时正在向上或向下拉动其输出总线的信号，并且当另一个单向总线中继器正在主动驱动其输出时，指示信号禁止一个单向总线中继器主动驱动其输出。

公开(公告)号：US4763105A

公开(公告)日：1988-08-09

申请号：US71671

申请日：1987-07-08

申请人： Yih-Chyun Jenq

发明人： Yih-Chyun Jenq

IPC分类号： G06F3/041 ,  G01R13/20 ,  G06F3/048 ,  G06F3/05 ,  H03M1/00 ,  H03M1/12 ,  H03M1/06

CPC分类号： H03M1/1061 ,  H03M1/1215

摘要： A digitizer system includes M digitizers, each producing a separate waveform data sequence representing a succession of instantaneous magnitudes of an input signal at sample times determined by a periodic clock signal. Transmission of the clock signal to each digitizer is delayed by a corresponding adjustable delay time so as to control the relative sample timing of the digitizers. To adjust sample timing, a sine wave signal is applied as the input signal to each digitizer such that the M digitizers produce M separate waveform data sequences in response to said input signal and the M data sequences are interleaved and windowed to form a single waveform data sequence. A first sequence of complex numbers representing a discrete Fourier transform of the single waveform data sequence is generated and then a second sequence of M complex numbers is formed from elements corresponding to relative magnitude peaks of the first sequence. A third sequence of M complex numbers is generated representing an inverse discrete Fourier transform of the second sequence and the phase angle of each number of the third sequence is computed and divided by the input signal frequency to produce a set of M numbers, each representing a timing error for a corresponding one of the M digitizers. The time delay corresponding to each digitizer is then adjusted by the amount of the timing error.

公开(公告)号：US5428800A

公开(公告)日：1995-06-27

申请号：US960965

申请日：1992-10-13

申请人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng ,  Keith Lofstrom

发明人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng ,  Keith Lofstrom

IPC分类号： H03K19/173 ,  G06F13/40 ,  H03K19/0175 ,  H03K19/177 ,  G06F13/00 ,  H03K17/16

CPC分类号： G06F13/4004 ,  H03K19/017581 ,  H03K19/01759

摘要： A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up. The bi-directional buffer includes a register for storing and reading out data representing successive logic states of a signal on the first bus, thereby providing a history of data appearing on the bus.

摘要翻译： 双向缓冲器包括第一和第二单向缓冲器，连接用于在第一和第二总线之间以相反方向重新发送信号。 当外部总线驱动器将第一总线拉低时，第一单向缓冲器将第二总线拉低，并产生禁止第二单向缓冲器主动驱动第一总线的信号。 当外部总线驱动器允许第一总线返回到高逻辑电平时，第一单向缓冲器临时向第二总线提供高充电电流，以快速将其拉起。 类似地，当外部总线驱动器将第二总线拉低时，第二单向缓冲器将第一总线拉低，并产生禁止第一单向缓冲器主动驱动第二总线的信号。 当外部总线驱动器允许第二总线返回到高逻辑电平时，第二缓冲器暂时向第一总线提供高充电电流以快速将其拉起。 双向缓冲器包括用于存储和读出表示第一总线上的信号的连续逻辑状态的数据的寄存器，从而提供出现在总线上的数据历史。

公开(公告)号：US5081592A

公开(公告)日：1992-01-14

申请号：US463828

申请日：1990-01-16

申请人： Yih-Chyun Jenq

发明人： Yih-Chyun Jenq

IPC分类号： G01R13/34 ,  G01R31/28 ,  G01R31/3167 ,  G01R31/3177 ,  G01R31/319 ,  G06F11/25 ,  G06F11/32 ,  G06F11/34

CPC分类号： G06F11/322 ,  G01R13/34 ,  G01R31/2834 ,  G01R31/2839 ,  G01R31/3167 ,  G01R31/3177 ,  G01R31/31912 ,  G06F11/25 ,  G06F11/34 ,  Y10S715/97

摘要： A system for testing electronic devices includes a waveform generator, a data acquisition system, and a computer. The waveform generator continuously generates a test signal having adjustable parameters set by the computer in response to user input. The data acquisition system acquires data representing the output of the device under test in response to the input signal and stores the last N acquired data values. The computer transfers a data sequence from the acquisition system to another memory and generates in a window on a terminal screen a wagveform display representing the stored data sequence. The computer also displays menu items referencing mathematical operations that may be performed on one or more data sequences. When a user selects one of the menu items, the computer prompts the user to select one or more windows containing waveform displays. Thereafter, the computer performs the selected operation on the data sequence controlling the waveform displays in the selected windows. When the result of the operation is a new data sequence, the computer stores the new data sequence in memory and then produces in a user-selected window a new waveform display based on the new data sequence.

摘要翻译： 用于测试电子设备的系统包括波形发生器，数据采集系统和计算机。 波形发生器连续地生成具有由计算机响应于用户输入设置的可调参数的测试信号。 数据采集​​系统响应于输入信号获取表示被测设备的输出的数据，并存储最后的N个获取的数据值。 计算机将数据序列从采集系统传送到另一个存储器，并在终端屏幕的窗口中生成表示所存储的数据序列的横图形显示。 计算机还显示参考可以在一个或多个数据序列上执行的数学运算的菜单项。 当用户选择其中一个菜单项时，计算机提示用户选择一个或多个包含波形显示的窗口。 此后，计算机对控制所选窗口中的波形显示的数据序列执行所选择的操作。 当操作结果是新的数据序列时，计算机将新的数据序列存储在存储器中，然后在用户选择的窗口中产生基于新的数据序列的新的波形显示。

公开(公告)号：US4791600A

公开(公告)日：1988-12-13

申请号：US890192

申请日：1986-07-28

申请人： Yih-Chyun Jenq

发明人： Yih-Chyun Jenq

IPC分类号： H04L27/00 ,  H03D7/00 ,  G06F7/52

CPC分类号： H03D7/00 ,  H03D2200/0056 ,  H03D2200/0072

摘要： A digital pipelined heterodyne circuit includes sine and cosine function generators for generating m-bit digital coefficients and an m-stage digital multiplier for multiplying the coefficients by a digitized data input signal. A triangular shift register array connects the digital sine and cosine function generators with the multiplier stages and provides for simultaneous processing of successive bytes of input data at each multiplier stage by delaying the arrival of coefficient bits at each multiplier stage to coincide with the arrival of a predetermined data byte. This takes place simultaneously in all stages thereby decreasing the processing time by a factor of m.

摘要翻译： 数字流水线外差电路包括用于产生m位数字系数的正弦和余弦函数发生器和用于将系数乘以数字化数据输入信号的m级数字乘法器。 三角形移位寄存器阵列将数字正弦和余弦函数发生器与乘法器级连接，并且通过在每个乘法器级延迟系数位的到达来提供在每个乘法器级同时处理输入数据的连续字节，以与一个 预定数据字节。 这在所有阶段同时进行，从而将处理时间减少了一个因子m。

公开(公告)号：US4825379A

公开(公告)日：1989-04-25

申请号：US901668

申请日：1986-08-29

申请人： Ajay K. Luthra ,  Yih-Chyun Jenq

发明人： Ajay K. Luthra ,  Yih-Chyun Jenq

IPC分类号： H04N5/93 ,  G01R13/32 ,  G01R13/34 ,  G06F17/10 ,  G06F17/15 ,  G11B5/00 ,  H04N17/06 ,  G01R25/00

CPC分类号： G01R13/345 ,  G01R13/32

摘要： Stored waveform records representative of respective repetitions of a repetitive signal are processed by reading a first waveform record from memory to form a reference signal. A second waveform record is read from memory to form a second signal, and the second signal is shifted in time in such a manner as to minimize the power of a difference signal, of which the instantaneous magnitude is representative of the difference in instantaneous magnitude between the reference signal and the time-shifted second signal. If the waveform records are identical but for jitter, and the power of the difference signal is brought to zero, this implies that the first waveform signal is synchronous with the processed second waveform signal, i.e., there is no jitter between the two signals. If waveform records resulting from the reference signal and the processed second signal are then averaged, the level of noise in the averaged record is reduced relative to the stored records and the averaged record is free of distortion due to jitter.

摘要翻译： 通过从存储器读取第一波形记录来形成参考信号来处理表示重复信号的相应重复的存储的波形记录。 从存储器读取第二波形记录以形成第二信号，并且第二信号以这样的方式在时间上移位，以使差分信号的功率最小化，其中瞬时幅度表示瞬时幅度之间的差异 参考信号和时移第二信号。 如果波形记录相同，但是对于抖动，并且差分信号的功率变为零，这意味着第一波形信号与处理的第二波形信号同步，即两个信号之间没有抖动。 如果从参考信号和经处理的第二信号得到的波形记录然后被平均，则平均记录中的噪声水平相对于存储的记录减小，并且平均记录由于抖动而没有失真。