Abstract:
A blood smear preparation device includes a base; a carrying table for carrying a microscope slide thereon and being supported on the base; a lifting mechanism mounted to the base; a retaining stand suspended from an output end of the lifting mechanism; a spreader holder rotatably suspended from the retaining stand about a second rotating shaft and positioned above the carrying table; a positioning member for positioning the spreader; and a torsion elastic member provided about the second rotating shaft, with a free end of the torsion elastic member abutting against the spreader holder. With the provision of the second rotating shaft and the torsion elastic member, the spreader has a certain degree of flexibility and self-adaptiveness. Even if the spreader or the microscope slide has no good micro-flatness or straightness, the device may automatically adjust the positions of the spreader and the microscope slide to achieve a line contact and a surface contact, and thus ensure the quality of the blood smear.
Abstract:
A blood smear preparation device includes a base; a carrying table for carrying a microscope slide thereon and being supported on the base; a lifting mechanism mounted to the base; a retaining stand suspended from an output end of the lifting mechanism; a spreader holder rotatably suspended from the retaining stand about a second rotating shaft and positioned above the carrying table; a positioning member for positioning the spreader; and a torsion elastic member provided about the second rotating shaft, with a free end of the torsion elastic member abutting against the spreader holder. With the provision of the second rotating shaft and the torsion elastic member, the spreader has a certain degree of flexibility and self-adaptiveness. Even if the spreader or the microscope slide has no good micro-flatness or straightness, the device may automatically adjust the positions of the spreader and the microscope slide to achieve a line contact and a surface contact, and thus ensure the quality of the blood smear.
Abstract:
Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.
Abstract:
In one embodiment, a method for transmitting information includes processing a downlink transport channel to generate a transport block (TB) having a TB size. The TB size is selected by selecting a modulation and coding scheme index (ITBS) and a physical resource block index (NPRB). The TB size for the selected ITBS and NPRB is selected so that an effective code rate at an user equipment (UE) does not exceed a specified threshold. The effective code rate is defined as a number of downlink (DL) information bits including TB cyclic redundancy check (CRC) bits and code block CRC bits divided by a number of physical channel bits on Physical Downlink Shared Channel (PDSCH). The transport block is mapped to multiple spatial layers. The number of spatial layers N is greater than or equal to three. The multiple spatial layers are transmitted to the UE.
Abstract:
Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.
Abstract:
Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.
Abstract:
A CMOS device has PMOS and NMOS transistors with different gate structures overlying a semiconductor device. A first gate structure overlying the PMOS device region has a first gate dielectric layer overlying the semiconductor substrate, and a first gate conductor overlying the first gate dielectric layer. A second gate device region overlying the NMOS device region has a second gate dielectric layer overlying the semiconductor substrate, and a second gate conductor overlying the first gate dielectric layer. The first gate conductor has a silicon-based material layer, and the second gate conductor has a metal-based material layer.
Abstract:
The embodiments of the present invention disclose an apparatus for transmitting multi-ary error-correcting codes, an apparatus for receiving multi-ary error-correcting codes, a data transmission system, and relevant methods to simplify operations. The apparatus for transmitting multi-ary error-correcting codes includes: a multi-ary channel encoder, adapted to perform multi-ary coding for source data frames of a user to obtain encoded sequences; a symbol mapper, adapted to perform symbol mapping for the encoded sequences to obtain symbol sequences; and a spreading and interleaving unit, adapted to spread and interleave the symbol sequences. Moreover, a corresponding apparatus for receiving multi-ary error-correcting codes, a data transmission system, and relevant methods are provided.
Abstract:
A system and method for system and method for multiplexing control and data channels in a multiple input, multiple output (MIMO) communications system are provided. A method for transmitting control symbols and data symbols on multiple MIMO layers includes selecting a first set of codewords from Ncw codewords, distributing control symbols onto the first set of layers, placing data symbols of the first set of codewords onto the first set of layers, placing data symbols of the (Ncw-Ncw1) remaining codewords to remaining layers if Ncw>Ncw1, and transmitting the multiple MIMO layers. The first set of codewords is associated with a first set of layers from the multiple MIMO layers, and the Ncw codewords are to be transmitted simultaneously and the first set of codewords comprises Ncw1 MIMO codewords, where Ncw and Ncw1 are integers greater than or equal to 1. The remaining layers are MIMO layers from the multiple MIMO layers not in the first set of layers.
Abstract:
A system and method for multiple input, multiple output (MIMO) uplink (UL) layer mapping is provided. A method for mapping modulation symbols to multiple input, multiple output (MIMO) layers includes receiving a first set of modulation symbols corresponding to a first transport block, partitioning the first set of modulation symbols into M1 parts, assigning each of the M1 parts to one of the M1 MIMO layers, and transmitting the modulation symbols mapped onto the M1 MIMO layers. The first transport block includes a plurality of code blocks, all modulation symbols of at least one code block belongs to a single part, and M1 is a positive integer value greater than one.