公开(公告)号：US08841181B2

公开(公告)日：2014-09-23

申请号：US13414375

申请日：2012-03-07

申请人： Ying-Hung Chou ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Zen-Jay Tsai ,  Shih-Hao Su ,  Chun-Chia Chen ,  Shih-Chieh Hsu ,  Chih-Chung Chen

发明人： Ying-Hung Chou ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Zen-Jay Tsai ,  Shih-Hao Su ,  Chun-Chia Chen ,  Shih-Chieh Hsu ,  Chih-Chung Chen

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.

摘要翻译： 对半导体装置的制造方法进行说明。 在衬底上形成栅极层，C掺杂的第一保护层和硬掩模层，然后图案化以在第一区域中形成第一堆叠，在第二区域中形成第二堆叠。 在第一和第二堆叠的侧壁上形成第二保护层。 阻挡层形成在第一区域中，第一隔离物形成在第二区域中的第二堆叠的侧壁上的第二保护层的侧壁上。 在第一间隔物旁边的基板中形成半导体化合物。 去除阻挡层和第一间隔物。 第一堆叠中的硬掩模层和第二堆叠被去除。

公开(公告)号：US20130234216A1

公开(公告)日：2013-09-12

申请号：US13414375

申请日：2012-03-07

申请人： Ying-Hung Chou ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Zen-Jay Tsai ,  Shih-Hao Su ,  Chun-Chia Chen ,  Shih-Chieh Hsu ,  Chih-Chung Chen

发明人： Ying-Hung Chou ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Zen-Jay Tsai ,  Shih-Hao Su ,  Chun-Chia Chen ,  Shih-Chieh Hsu ,  Chih-Chung Chen

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.

摘要翻译： 对半导体装置的制造方法进行说明。 在衬底上形成栅极层，C掺杂的第一保护层和硬掩模层，然后图案化以在第一区域中形成第一堆叠，在第二区域中形成第二堆叠。 在第一和第二堆叠的侧壁上形成第二保护层。 阻挡层形成在第一区域中，第一隔离物形成在第二区域中的第二堆叠的侧壁上的第二保护层的侧壁上。 在第一间隔物旁边的基板中形成半导体化合物。 去除阻挡层和第一间隔物。 第一堆叠中的硬掩模层和第二堆叠被去除。

公开(公告)号：US20130137256A1

公开(公告)日：2013-05-30

申请号：US13304416

申请日：2011-11-25

申请人： Zen-Jay Tsai ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Ying-Hung Chou ,  Shih-Hao Su ,  Shih-Chieh Hsu ,  Chih-Ho Wang ,  Hung-Yi Wu ,  Shui-Yen Lu

发明人： Zen-Jay Tsai ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Ying-Hung Chou ,  Shih-Hao Su ,  Shih-Chieh Hsu ,  Chih-Ho Wang ,  Hung-Yi Wu ,  Shui-Yen Lu

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

摘要： A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.

摘要翻译： 提供半导体工艺。 前述步骤包括：在基板上形成包括第一盖层的第一栅极和包括第二盖层的第二栅极。 形成硬掩模层以覆盖第一栅极和第二栅极。 硬掩模层的材料与第一盖层和第二盖层的材料不同。 在光刻工艺和蚀刻工艺进行之后，硬掩模层被完全去除。 以下步骤包括：形成材料以完全覆盖第一栅极和第二栅极。 材料，第一栅极和第二栅极被回蚀，以使第一栅极和第二栅极具有相同的电平并且在它们两者中暴露层。

公开(公告)号：US08709930B2

公开(公告)日：2014-04-29

申请号：US13304416

申请日：2011-11-25

申请人： Zen-Jay Tsai ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Ying-Hung Chou ,  Shih-Hao Su ,  Shih-Chieh Hsu ,  Chih-Ho Wang ,  Hung-Yi Wu ,  Shui-Yen Lu

发明人： Zen-Jay Tsai ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Ying-Hung Chou ,  Shih-Hao Su ,  Shih-Chieh Hsu ,  Chih-Ho Wang ,  Hung-Yi Wu ,  Shui-Yen Lu

IPC分类号： H01L21/3205

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

摘要： A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.

摘要翻译： 提供半导体工艺。 前述步骤包括：在基板上形成包括第一盖层的第一栅极和包括第二盖层的第二栅极。 形成硬掩模层以覆盖第一栅极和第二栅极。 硬掩模层的材料与第一盖层和第二盖层的材料不同。 在光刻工艺和蚀刻工艺进行之后，硬掩模层被完全去除。 以下步骤包括：形成材料以完全覆盖第一栅极和第二栅极。 材料，第一栅极和第二栅极被回蚀，以使第一栅极和第二栅极具有相同的电平并且在它们两者中暴露层。

公开(公告)号：US08278166B2

公开(公告)日：2012-10-02

申请号：US12837519

申请日：2010-07-16

申请人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

发明人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

摘要： A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

摘要翻译： 制造CMOS器件的方法包括提供具有第一区域和第二区域的衬底; 形成第一栅极结构和第二栅极结构，每个栅极结构包括牺牲层和硬掩模层; 形成覆盖所述第一区域的图案化的第一保护层和在所述第二栅极结构的侧壁上的第一间隔物; 进行蚀刻工艺以在基板中形成第一凹部; 执行SEG工艺以在每个第一凹部中形成外延硅层; 形成覆盖所述第二区域的图案化的第二保护层; 以及利用所述图案化的第二保护层作为蚀刻掩模进行干蚀刻工艺，以蚀刻所述图案化的第一保护层，以在所述第一栅极结构的侧壁上形成第二间隔物，并且使所述第一栅极结构上的所述硬掩模层变薄 。

公开(公告)号：US20120012938A1

公开(公告)日：2012-01-19

申请号：US12837519

申请日：2010-07-16

申请人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

发明人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

摘要： A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

摘要翻译： 制造CMOS器件的方法包括提供具有第一区域和第二区域的衬底; 形成第一栅极结构和第二栅极结构，每个栅极结构包括牺牲层和硬掩模层; 形成覆盖所述第一区域的图案化的第一保护层和在所述第二栅极结构的侧壁上的第一间隔物; 进行蚀刻工艺以在基板中形成第一凹部; 执行SEG工艺以在每个第一凹槽中形成外延硅层; 形成覆盖所述第二区域的图案化的第二保护层; 以及利用所述图案化的第二保护层作为蚀刻掩模进行干蚀刻工艺，以蚀刻所述图案化的第一保护层，以在所述第一栅极结构的侧壁上形成第二间隔物，并且使所述第一栅极结构上的所述硬掩模层变薄 。

公开(公告)号：US08981527B2

公开(公告)日：2015-03-17

申请号：US13215237

申请日：2011-08-23

申请人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

发明人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

IPC分类号： H01L21/8234 ,  H01L49/02 ,  H01L27/06

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

摘要翻译： 一种用于形成与具有金属栅极的晶体管集成的电阻器的方法包括提供具有限定在其上的晶体管区域和电阻器区域的衬底，在晶体管区域中形成具有多晶硅虚拟栅极的晶体管，以及多晶硅主体部分，其中两个掺杂区域 在电阻器区域的两个相对端处，执行蚀刻工艺以去除多晶硅虚拟栅极以形成第一沟槽并去除掺杂区域的部分以形成两个第二沟槽，并且在第一沟槽中形成金属栅极以形成晶体管 在第二沟槽中分别具有金属栅极和金属结构以形成电阻器。

公开(公告)号：US20130049168A1

公开(公告)日：2013-02-28

申请号：US13215237

申请日：2011-08-23

申请人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

发明人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

IPC分类号： H01L21/8234 ,  H01L27/06

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

摘要翻译： 一种用于形成与具有金属栅极的晶体管集成的电阻器的方法包括提供具有限定在其上的晶体管区域和电阻器区域的衬底，在晶体管区域中形成具有多晶硅虚拟栅极的晶体管，以及多晶硅主体部分，其中两个掺杂区域 在电阻器区域的两个相对端处，执行蚀刻工艺以去除多晶硅虚拟栅极以形成第一沟槽并去除掺杂区域的部分以形成两个第二沟槽，并且在第一沟槽中形成金属栅极以形成晶体管 在第二沟槽中分别具有金属栅极和金属结构以形成电阻器。

公开(公告)号：US20060085448A1

公开(公告)日：2006-04-20

申请号：US11004957

申请日：2004-12-07

申请人： Ming-Hung Hsieh ,  Ying-Hung Chou

发明人： Ming-Hung Hsieh ,  Ying-Hung Chou

IPC分类号： G06F7/00

CPC分类号： G06F8/30

摘要： According to the method of the present invention, first, the code of the program language used to develop a web page is classified and rearranged. Next, the rearranged program code is transferred to another program code with similar syntax. Then, the transferred code is compiled to generate an object file and a web page program file.

摘要翻译： 根据本发明的方法，首先分类和重新排列用于开发网页的程序语言的代码。 接下来，将重新排列的程序代码转移到具有相似语法的另一程序代码。 然后，转移的代码被编译成生成目标文件和网页程序文件。