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    Method of manufacturing complementary metal oxide semiconductor device
    5.
    发明授权
    Method of manufacturing complementary metal oxide semiconductor device 有权
    互补金属氧化物半导体器件的制造方法

    公开(公告)号：US08278166B2

    公开(公告)日：2012-10-02

    申请号：US12837519

    申请日：2010-07-16

    申请人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

    发明人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

    摘要： A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

    摘要翻译： 制造CMOS器件的方法包括提供具有第一区域和第二区域的衬底; 形成第一栅极结构和第二栅极结构，每个栅极结构包括牺牲层和硬掩模层; 形成覆盖所述第一区域的图案化的第一保护层和在所述第二栅极结构的侧壁上的第一间隔物; 进行蚀刻工艺以在基板中形成第一凹部; 执行SEG工艺以在每个第一凹部中形成外延硅层; 形成覆盖所述第二区域的图案化的第二保护层; 以及利用所述图案化的第二保护层作为蚀刻掩模进行干蚀刻工艺，以蚀刻所述图案化的第一保护层，以在所述第一栅极结构的侧壁上形成第二间隔物，并且使所述第一栅极结构上的所述硬掩模层变薄 。

    METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE 有权
    制备补充金属氧化物半导体器件的方法

    公开(公告)号：US20120012938A1

    公开(公告)日：2012-01-19

    申请号：US12837519

    申请日：2010-07-16

    申请人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

    发明人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

    摘要： A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

    摘要翻译： 制造CMOS器件的方法包括提供具有第一区域和第二区域的衬底; 形成第一栅极结构和第二栅极结构，每个栅极结构包括牺牲层和硬掩模层; 形成覆盖所述第一区域的图案化的第一保护层和在所述第二栅极结构的侧壁上的第一间隔物; 进行蚀刻工艺以在基板中形成第一凹部; 执行SEG工艺以在每个第一凹槽中形成外延硅层; 形成覆盖所述第二区域的图案化的第二保护层; 以及利用所述图案化的第二保护层作为蚀刻掩模进行干蚀刻工艺，以蚀刻所述图案化的第一保护层，以在所述第一栅极结构的侧壁上形成第二间隔物，并且使所述第一栅极结构上的所述硬掩模层变薄 。

    RESISTOR AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    RESISTOR AND MANUFACTURING METHOD THEREOF 有权
    电阻及其制造方法

    公开(公告)号：US20130049168A1

    公开(公告)日：2013-02-28

    申请号：US13215237

    申请日：2011-08-23

    申请人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

    发明人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

    IPC分类号： H01L21/8234 ,  H01L27/06

    CPC分类号： H01L28/20 ,  H01L27/0629

    摘要： A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

    摘要翻译： 一种用于形成与具有金属栅极的晶体管集成的电阻器的方法包括提供具有限定在其上的晶体管区域和电阻器区域的衬底，在晶体管区域中形成具有多晶硅虚拟栅极的晶体管，以及多晶硅主体部分，其中两个掺杂区域 在电阻器区域的两个相对端处，执行蚀刻工艺以去除多晶硅虚拟栅极以形成第一沟槽并去除掺杂区域的部分以形成两个第二沟槽，并且在第一沟槽中形成金属栅极以形成晶体管 在第二沟槽中分别具有金属栅极和金属结构以形成电阻器。

    Resistor and manufacturing method thereof
    8.
    发明授权
    Resistor and manufacturing method thereof 有权
    电阻及其制造方法

    公开(公告)号：US08981527B2

    公开(公告)日：2015-03-17

    申请号：US13215237

    申请日：2011-08-23

    申请人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

    发明人： Jie-Ning Yang ,  Shih-Chieh Hsu ,  Yao-Chang Wang ,  Chi-Horn Pai ,  Chi-Sheng Tseng ,  Kun-Szu Tseng ,  Ying-Hung Chou ,  Chiu-Hsien Yeh

    IPC分类号： H01L21/8234 ,  H01L49/02 ,  H01L27/06

    CPC分类号： H01L28/20 ,  H01L27/0629

    摘要： A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

    摘要翻译： 一种用于形成与具有金属栅极的晶体管集成的电阻器的方法包括提供具有限定在其上的晶体管区域和电阻器区域的衬底，在晶体管区域中形成具有多晶硅虚拟栅极的晶体管，以及多晶硅主体部分，其中两个掺杂区域 在电阻器区域的两个相对端处，执行蚀刻工艺以去除多晶硅虚拟栅极以形成第一沟槽并去除掺杂区域的部分以形成两个第二沟槽，并且在第一沟槽中形成金属栅极以形成晶体管 在第二沟槽中分别具有金属栅极和金属结构以形成电阻器。

    Method for fabricating a semiconductor device
    9.
    发明授权
    Method for fabricating a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US08207043B2

    公开(公告)日：2012-06-26

    申请号：US12568657

    申请日：2009-09-28

    申请人： Huang-Yi Lin ,  Jiun-Hung Shen ,  Chi-Horn Pai ,  Yi-Chung Sheng ,  Shih-Chieh Hsu

    发明人： Huang-Yi Lin ,  Jiun-Hung Shen ,  Chi-Horn Pai ,  Yi-Chung Sheng ,  Shih-Chieh Hsu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7847

    摘要： A method for making a semiconductor MOS device is provided. A gate structure is formed on a substrate. A source and a drain are formed in the substrate on both sides of the gate structure. The substrate is then subjected to a pre-amorphization implant (PAI) process. A transitional stress layer is then formed on the substrate. Thereafter, a laser anneal with a first temperature is performed. After the laser anneal, a rapid thermal process is performed with a second temperature that is lower than the first temperature. Subsequently, the transitional stress layer is removed.

    摘要翻译： 提供了制造半导体MOS器件的方法。 在基板上形成栅极结构。 源极和漏极形成在栅极结构两侧的衬底中。 然后将基材进行预非晶化植入（PAI）工艺。 然后在衬底上形成过渡应力层。 此后，进行具有第一温度的激光退火。 在激光退火之后，以低于第一温度的第二温度进行快速热处理。 随后，去除过渡应力层。