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6 条记录 (耗时 0.031 秒)

    Electron beam generating apparatus
    2.
    发明授权
    Electron beam generating apparatus 有权
    电子束发生装置

    公开(公告)号：US08736169B2

    公开(公告)日：2014-05-27

    申请号：US13122109

    申请日：2010-08-10

    申请人： Yong Woon Park ,  Sung Ju Park ,  In Soo Ko ,  Chang Bum Kim ,  Ju Ho Hong ,  Sung Ik Moon

    发明人： Yong Woon Park ,  Sung Ju Park ,  In Soo Ko ,  Chang Bum Kim ,  Ju Ho Hong ,  Sung Ik Moon

    IPC分类号： H01J29/80

    CPC分类号： H01J3/02

    摘要： An apparatus for generating an electron beam is disclosed to reduce emittance of an electron beam. The apparatus includes: a housing including a rear portion where an electron beam is generated, a front portion having an electron beam discharge hole for discharging the electron beam to the exterior, and a side portion connecting the rear portion and the front portion, the side portion having a first hole and an opposite side portion, facing the first hole, having a second hole in order to reduce asymmetry of an electric field caused by the first hole; and a waveguide installed on the side portion to supply an electromagnetic wave to the interior of the housing through the first hole, wherein the electron beam is generated by laser incident to the interior of the housing and accelerated by the electromagnetic wave supplied to the interior of the housing.

    摘要翻译： 公开了一种用于产生电子束的装置，以减少电子束的发射。 该装置包括：壳体，其包括产生电子束的后部，具有用于将电子束排出到外部的电子束排出孔的前部和连接后部和前部的侧部， 具有第一孔和与第一孔相对的相对侧部的部分具有第二孔，以减少由第一孔引起的电场的不对称性; 以及安装在所述侧部上的波导，以通过所述第一孔向所述壳体的内部提供电磁波，其中所述电子束通过入射到所述壳体的内部的激光产生并且被提供给所述壳体内部的电磁波加速 住房。

    ELECTRON BEAM GENERATING APPARATUS
    3.
    发明申请
    ELECTRON BEAM GENERATING APPARATUS 有权
    电子束发生装置

    公开(公告)号：US20120133281A1

    公开(公告)日：2012-05-31

    申请号：US13122109

    申请日：2010-08-10

    申请人： Yong Woon Park ,  Sung Ju Park ,  In Soo Ko ,  Chang Bum Kim ,  Ju Ho Hong ,  Sung Ik Moon

    发明人： Yong Woon Park ,  Sung Ju Park ,  In Soo Ko ,  Chang Bum Kim ,  Ju Ho Hong ,  Sung Ik Moon

    IPC分类号： H01J29/80

    CPC分类号： H01J3/02

    摘要： An apparatus for generating an electron beam is disclosed to reduce emittance of an electron beam. The apparatus includes: a housing including a rear portion where an electron beam is generated, a front portion having an electron beam discharge hole for discharging the electron beam to the exterior, and a side portion connecting the rear portion and the front portion, the side portion having a first hole and an opposite side portion, facing the first hole, having a second hole in order to reduce asymmetry of an electric field caused by the first hole; and a waveguide installed on the side portion to supply an electromagnetic wave to the interior of the housing through the first hole, wherein the electron beam is generated by laser incident to the interior of the housing and accelerated by the electromagnetic wave supplied to the interior of the housing.

    摘要翻译： 公开了一种用于产生电子束的装置，以减少电子束的发射。 该装置包括：壳体，其包括产生电子束的后部，具有用于将电子束排出到外部的电子束排出孔的前部和连接后部和前部的侧部， 具有第一孔和与第一孔相对的相对侧部的部分具有第二孔，以减少由第一孔引起的电场的不对称性; 以及安装在所述侧部上的波导，以通过所述第一孔向所述壳体的内部提供电磁波，其中所述电子束通过入射到所述壳体的内部的激光产生并且被提供给所述壳体内部的电磁波加速 住房。

    Wrapped core linking module for accessing system on chip test
    4.
    发明授权
    Wrapped core linking module for accessing system on chip test 失效
    包裹核心链接模块，用于访问片上系统测试

    公开(公告)号：US07117413B2

    公开(公告)日：2006-10-03

    申请号：US10284123

    申请日：2002-10-31

    申请人： Chang Won Park ,  Sung Ju Park ,  Hyung Su Lee ,  Jae Hoon Song

    发明人： Chang Won Park ,  Sung Ju Park ,  Hyung Su Lee ,  Jae Hoon Song

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318558 ,  G01R31/318508 ,  G01R31/318555 ,  G01R31/318563

    摘要： A wrapped core linking module for accessing system on chip test includes a link control register that stores link control configuration between cores in a scan path of a system on chip according to control signals applied from an outside boundary. A link control register controller controls a shift and update link configuration by activating the link control register. A switch switches the scan path between wrapped cores based on the link control configuration of the link control register. An output logic connects the link control register to a test data out (TDO) of the chip in case of testing on chip or cores of system on chip.

    摘要翻译： 用于访问片上测试的包裹核心链接模块包括链路控制寄存器，其根据从外部边界施加的控制信号在片上系统的扫描路径中存储核心之间的链路控制配置。 链路控制寄存器控制器通过激活链路控制寄存器来控制移位和更新链路配置。 交换机根据链路控制寄存器的链路控制配置切换包裹核心之间的扫描路径。 输出逻辑将链路控制寄存器连接到片上芯片或芯片上的芯片的测试数据输出（TDO）。

    Interconnect delay fault test controller and test apparatus using the same
    5.
    发明授权
    Interconnect delay fault test controller and test apparatus using the same 失效
    互连延迟故障测试控制器和使用其的测试仪器

    公开(公告)号：US07673203B2

    公开(公告)日：2010-03-02

    申请号：US11616471

    申请日：2006-12-27

    申请人： Chang Won Park ,  Ki Man Jeon ,  Young Hwan Kim ,  Jae Gi Son ,  Hyun Bean Yi ,  Sung Ju Park

    发明人： Chang Won Park ,  Ki Man Jeon ,  Young Hwan Kim ,  Jae Gi Son ,  Hyun Bean Yi ,  Sung Ju Park

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31725 ,  G01R31/31855

    摘要： An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.

    摘要翻译： 一种互连延迟故障测试控制器和使用该互连延迟故障测试控制器的测试装置，其中当在IEEE P1500封装核心之间执行互连延迟故障测试时，可以在系统时钟或核心时钟的一个间隔中执行更新操作和捕获操作 在SoC以及基于IEEE 1149.1的板上的互连线，并且其中使用不同系统时钟或核心时钟的互连延迟故障测试可以在对应于每个系统时钟或核心时钟的一个测试周期中同时执行，甚至 当公开了多个系统时钟或核心时钟时。

    Soc-based core scan chain linkage switch
    6.
    发明授权
    Soc-based core scan chain linkage switch 失效
    基于Soc的核心扫描链联动开关

    公开(公告)号：US07296200B2

    公开(公告)日：2007-11-13

    申请号：US10995099

    申请日：2004-11-24

    申请人： Chang Won Park ,  Ki Man Jeon ,  Sung Ju Park ,  Kyeong Won Yeom ,  Tae Sik Kim

    发明人： Chang Won Park ,  Ki Man Jeon ,  Sung Ju Park ,  Kyeong Won Yeom ,  Tae Sik Kim

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318558

    摘要： Disclosed herein is an SoC-based core scan chain linkage switch. The core scan chain linkage switch includes test bus terminals, scan chain input/output terminals, a switch unit and SCLK, UCLK, Mode and Enable signals. The test bus terminals apply instructions and input/output test data. The scan chain input/output terminals link with the scan chains of an embedded core. The switch unit completes a linkage configuration between the test bus terminals and the scan chain input/output terminals in response to the applied instructions. The SCLK, UCLK and Mode signals apply the instructions to dynamically reconfigure the switch unit and update the linkage configuration of the switch unit, and the Enable signal activates and deactivates the switch unit.

    摘要翻译： 这里公开了一种基于SoC的核心扫描链接开关。 核心扫描链联动开关包括测试总线端子，扫描链输入/输出端子，开关单元和SCLK，UCLK，模式和使能信号。 测试总线终端应用指令和输入/输出测试数据。 扫描链输入/输出端子与嵌入式核心的扫描链连接。 开关单元响应于所施加的指令，在测试总线端子和扫描链输入/输出端子之间完成连接配置。 SCLK，UCLK和模式信号应用指令来动态地重新配置开关单元并更新开关单元的联动配置，使能信号激活和停用开关单元。