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    Semiconductor device isolation structures and methods of fabricating such structures
    1.
    发明授权
    Semiconductor device isolation structures and methods of fabricating such structures 有权
    半导体器件隔离结构及其制造方法

    公开(公告)号：US07674685B2

    公开(公告)日：2010-03-09

    申请号：US11654588

    申请日：2007-01-18

    申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

    摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

    摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

    Semiconductor device isolation structures and methods of fabricating such structures
    3.
    发明申请
    Semiconductor device isolation structures and methods of fabricating such structures 有权
    半导体器件隔离结构及其制造方法

    公开(公告)号：US20080014711A1

    公开(公告)日：2008-01-17

    申请号：US11654588

    申请日：2007-01-18

    申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

    摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

    摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

    Flash memory device and method of fabricating the same
    4.
    发明授权
    Flash memory device and method of fabricating the same 有权
    闪存装置及其制造方法

    公开(公告)号：US07842569B2

    公开(公告)日：2010-11-30

    申请号：US11618155

    申请日：2006-12-29

    申请人： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

    摘要翻译： 制造闪速存储器件的方法的一个实施例包括在半导体衬底上形成沟槽掩模图案，其包括依次层叠的栅极绝缘图案和电荷存储图案; 使用沟槽掩模图案作为蚀刻掩模蚀刻半导体衬底，以形成限定有源区的沟槽; 并且顺序地形成沟槽中的下部和上部器件隔离图案。 在上部器件隔离图案上顺序地形成栅极间绝缘膜和控制栅极膜之后，形成控制栅极膜，栅极间绝缘图案和阴极管栅极图案，从而提供跨越有源区域的栅极线。

    Semiconductor device having trench isolation region and methods of fabricating the same
    5.
    发明授权
    Semiconductor device having trench isolation region and methods of fabricating the same 有权
    具有沟槽隔离区域的半导体器件及其制造方法

    公开(公告)号：US07781304B2

    公开(公告)日：2010-08-24

    申请号：US12216820

    申请日：2008-07-11

    申请人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    发明人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229

    摘要： A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively.

    摘要翻译： 提供了具有沟槽隔离区域的半导体器件及其制造方法。 该方法包括在衬底中形成第一沟槽区域和在衬底中具有比第一沟槽区域宽的宽度的第二沟槽区域。 下部材料层可以填充第一和第二沟槽区域。 可以通过第一蚀刻工艺蚀刻下部材料层，以形成残留在第一沟槽区域中的第一初步下部材料层图案，并形成保留在第二沟槽区域中的第二预备下部材料层图案。 第二初步下层材料层图案的上表面可以处于与第一预备下层材料层图案不同的高度。 可以通过第二蚀刻工艺蚀刻第一和第二初级下部材料层图案，以形成具有基本上相同高度的顶表面的第一和第二下部材料层图案。 可以分别在第一和第二下部材料层图案上形成第一和第二上部材料层图案。

    Semiconductor device having trench isolation region and methods of fabricating the same
    6.
    发明申请
    Semiconductor device having trench isolation region and methods of fabricating the same 有权
    具有沟槽隔离区域的半导体器件及其制造方法

    公开(公告)号：US20090020847A1

    公开(公告)日：2009-01-22

    申请号：US12216820

    申请日：2008-07-11

    申请人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    发明人： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

    IPC分类号： H01L21/762 ,  H01L23/58

    CPC分类号： H01L21/76229

    摘要： A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively.

    摘要翻译： 提供了具有沟槽隔离区域的半导体器件及其制造方法。 该方法包括在衬底中形成第一沟槽区域和在衬底中具有比第一沟槽区域宽的宽度的第二沟槽区域。 下部材料层可以填充第一和第二沟槽区域。 可以通过第一蚀刻工艺蚀刻下部材料层，以形成残留在第一沟槽区域中的第一初步下部材料层图案，并形成保留在第二沟槽区域中的第二预备下部材料层图案。 第二初步下层材料层图案的上表面可以处于与第一预备下层材料层图案不同的高度。 可以通过第二蚀刻工艺蚀刻第一和第二初级下部材料层图案，以形成具有基本上相同高度的顶表面的第一和第二下部材料层图案。 可以分别在第一和第二下部材料层图案上形成第一和第二上部材料层图案。

    Method of forming an isolation layer and method of manufacturing a field effect transistor using the same
    7.
    发明申请
    Method of forming an isolation layer and method of manufacturing a field effect transistor using the same 审中-公开
    形成隔离层的方法和使用其形成场效应晶体管的方法

    公开(公告)号：US20070020879A1

    公开(公告)日：2007-01-25

    申请号：US11484574

    申请日：2006-07-12

    申请人： Eun-Kyung Baek ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Hong-Gun Kim ,  Kyu-Tae Na

    发明人： Eun-Kyung Baek ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Hong-Gun Kim ,  Kyu-Tae Na

    IPC分类号： H01L21/8234 ,  H01L21/76 ,  H01L21/336

    CPC分类号： H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

    摘要： In a method of forming a device isolation layer, a trench is formed in a substrate and a preliminary fin is formed on the substrate using a hard mask pattern on a surface of the substrate as an etching mask. A first thin layer is formed on the bottom and sides of the trench. A lower insulation pattern is formed in a lower portion of the trench on the first thin layer, and an upper insulation pattern is formed on the lower insulation pattern. The upper insulation pattern is etched away so that the first thin layer remains on a side surface of the preliminary fin. A device isolation layer is formed in the lower portion of the trench and a silicon fin is formed having a top surface thereof that is higher relative to a top surface of the device isolation layer.

    摘要翻译： 在形成器件隔离层的方法中，在衬底中形成沟槽，并且使用在衬底的表面上的硬掩模图案作为蚀刻掩模在衬底上形成预备鳍。 第一薄层形成在沟槽的底部和侧面上。 在第一薄层上的沟槽的下部形成下部绝缘图案，并且在下部绝缘图案上形成上部绝缘图案。 蚀刻掉上绝缘图案，使得第一薄层保留在预备翅片的侧表面上。 器件隔离层形成在沟槽的下部，并且形成硅片，其顶表面相对于器件隔离层的顶表面较高。

    Method of manufacturing a non-volatile semiconductor device
    8.
    发明申请
    Method of manufacturing a non-volatile semiconductor device 审中-公开
    制造非易失性半导体器件的方法

    公开(公告)号：US20070004139A1

    公开(公告)日：2007-01-04

    申请号：US11474428

    申请日：2006-06-26

    申请人： Hong-Gun Kim ,  Kyu-Tae Na ,  Eun-Kyung Baek ,  Ju-Seon Goo ,  Sang-Ho Rha

    发明人： Hong-Gun Kim ,  Kyu-Tae Na ,  Eun-Kyung Baek ,  Ju-Seon Goo ,  Sang-Ho Rha

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L21/7624 ,  H01L27/11521

    摘要： In a method of manufacturing a non-volatile semiconductor device, a mask structure is formed on a substrate. A trench is formed by partially etching the substrate using the mask structure. A preliminary isolation layer pattern is formed on the substrate to fill the trench. The preliminary isolation layer has an upper face lower than that of the mask structure. A capping layer pattern is formed on the preliminary isolation layer pattern. An opening and an isolation layer pattern are formed by removing the mask structure and a portion on a sidewall of the preliminary isolation layer pattern adjacent to the mask structure. After forming a tunnel oxide layer, a floating gate is formed on the tunnel oxide layer and a sidewall of the isolation layer pattern.

    摘要翻译： 在制造非挥发性半导体器件的方法中，在衬底上形成掩模结构。 通过使用掩模结构部分地蚀刻衬底来形成沟槽。 在衬底上形成初步隔离层图形以填充沟槽。 预备隔离层的上表面比掩模结构的上面低。 在初步隔离层图案上形成覆盖层图案。 通过去除掩模结构和邻近掩模结构的预隔离层图案的侧壁上的部分形成开口和隔离层图案。 在形成隧道氧化物层之后，在隧道氧化物层和隔离层图案的侧壁上形成浮栅。

    Semiconductor devices having trench isolation regions and methods of manufacturing semiconductor devices having trench isolation regions
    10.
    发明申请
    Semiconductor devices having trench isolation regions and methods of manufacturing semiconductor devices having trench isolation regions 审中-公开
    具有沟槽隔离区域的半导体器件和制造具有沟槽隔离区域的半导体器件的方法

    公开(公告)号：US20090045483A1

    公开(公告)日：2009-02-19

    申请号：US12222630

    申请日：2008-08-13

    申请人： Sang-Ho Rha ,  Eun-Kee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek

    发明人： Sang-Ho Rha ,  Eun-Kee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek

    IPC分类号： H01L21/762 ,  H01L23/58

    CPC分类号： H01L21/76232

    摘要： A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region.

    摘要翻译： 半导体器件可以包括半导体衬底，沟槽区，缓冲图案，间隙填充层和晶体管。 沟槽区域可以设置在半导体衬底中以限定有源区域。 缓冲图案和间隙填充层可以设置在沟槽区域中。 缓冲图案和间隙填充层可以填充沟槽区域。 间隙填充层可以由缓冲图案致密化。 晶体管可以设置在有源区中。 半导体器件的制造方法可以包括：在半导体衬底中形成沟槽区域; 在所述第一沟槽区的内壁上形成缓冲层; 形成间隙填充层，填充沟槽区域; 进行热处理以使杂质与氧反应，形成缓冲图案; 以及在有源区中形成晶体管。