公开(公告)号：US20080014711A1

公开(公告)日：2008-01-17

申请号：US11654588

申请日：2007-01-18

申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

公开(公告)号：US07674685B2

公开(公告)日：2010-03-09

申请号：US11654588

申请日：2007-01-18

申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

公开(公告)号：US20080121977A1

公开(公告)日：2008-05-29

申请号：US11699419

申请日：2007-01-30

申请人： Yong-Soon Choi ,  Hong-Gun Kim ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Ju-Seon Goo

发明人： Yong-Soon Choi ,  Hong-Gun Kim ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Ju-Seon Goo

IPC分类号： H01L29/788 ,  H01L21/04

CPC分类号： H01L21/76224 ,  H01L27/11521 ,  H01L29/7881

摘要： A semiconductor device includes a substrate having a trench, a liner layer pattern on sidewalls and a bottom surface of the trench, the liner layer pattern including a first oxide layer pattern and a second oxide layer pattern, a diffusion blocking layer pattern on the liner layer pattern, and an isolation layer pattern in the trench on the diffusion blocking layer pattern.

摘要翻译： 半导体器件包括具有沟槽的衬底，侧壁上的衬垫层图案和沟槽的底表面，衬里层图案包括第一氧化物层图案和第二氧化物层图案，衬垫层上的扩散阻挡层图案 图案和扩散阻挡层图案上的沟槽中的隔离层图案。

公开(公告)号：US07842569B2

公开(公告)日：2010-11-30

申请号：US11618155

申请日：2006-12-29

申请人： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

发明人： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

IPC分类号： H01L21/00

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

摘要翻译： 制造闪速存储器件的方法的一个实施例包括在半导体衬底上形成沟槽掩模图案，其包括依次层叠的栅极绝缘图案和电荷存储图案; 使用沟槽掩模图案作为蚀刻掩模蚀刻半导体衬底，以形成限定有源区的沟槽; 并且顺序地形成沟槽中的下部和上部器件隔离图案。 在上部器件隔离图案上顺序地形成栅极间绝缘膜和控制栅极膜之后，形成控制栅极膜，栅极间绝缘图案和阴极管栅极图案，从而提供跨越有源区域的栅极线。

公开(公告)号：US20070020879A1

公开(公告)日：2007-01-25

申请号：US11484574

申请日：2006-07-12

申请人： Eun-Kyung Baek ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Hong-Gun Kim ,  Kyu-Tae Na

发明人： Eun-Kyung Baek ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Hong-Gun Kim ,  Kyu-Tae Na

IPC分类号： H01L21/8234 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

摘要： In a method of forming a device isolation layer, a trench is formed in a substrate and a preliminary fin is formed on the substrate using a hard mask pattern on a surface of the substrate as an etching mask. A first thin layer is formed on the bottom and sides of the trench. A lower insulation pattern is formed in a lower portion of the trench on the first thin layer, and an upper insulation pattern is formed on the lower insulation pattern. The upper insulation pattern is etched away so that the first thin layer remains on a side surface of the preliminary fin. A device isolation layer is formed in the lower portion of the trench and a silicon fin is formed having a top surface thereof that is higher relative to a top surface of the device isolation layer.

摘要翻译： 在形成器件隔离层的方法中，在衬底中形成沟槽，并且使用在衬底的表面上的硬掩模图案作为蚀刻掩模在衬底上形成预备鳍。 第一薄层形成在沟槽的底部和侧面上。 在第一薄层上的沟槽的下部形成下部绝缘图案，并且在下部绝缘图案上形成上部绝缘图案。 蚀刻掉上绝缘图案，使得第一薄层保留在预备翅片的侧表面上。 器件隔离层形成在沟槽的下部，并且形成硅片，其顶表面相对于器件隔离层的顶表面较高。

公开(公告)号：US20070004139A1

公开(公告)日：2007-01-04

申请号：US11474428

申请日：2006-06-26

申请人： Hong-Gun Kim ,  Kyu-Tae Na ,  Eun-Kyung Baek ,  Ju-Seon Goo ,  Sang-Ho Rha

发明人： Hong-Gun Kim ,  Kyu-Tae Na ,  Eun-Kyung Baek ,  Ju-Seon Goo ,  Sang-Ho Rha

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/7624 ,  H01L27/11521

摘要： In a method of manufacturing a non-volatile semiconductor device, a mask structure is formed on a substrate. A trench is formed by partially etching the substrate using the mask structure. A preliminary isolation layer pattern is formed on the substrate to fill the trench. The preliminary isolation layer has an upper face lower than that of the mask structure. A capping layer pattern is formed on the preliminary isolation layer pattern. An opening and an isolation layer pattern are formed by removing the mask structure and a portion on a sidewall of the preliminary isolation layer pattern adjacent to the mask structure. After forming a tunnel oxide layer, a floating gate is formed on the tunnel oxide layer and a sidewall of the isolation layer pattern.

摘要翻译： 在制造非挥发性半导体器件的方法中，在衬底上形成掩模结构。 通过使用掩模结构部分地蚀刻衬底来形成沟槽。 在衬底上形成初步隔离层图形以填充沟槽。 预备隔离层的上表面比掩模结构的上面低。 在初步隔离层图案上形成覆盖层图案。 通过去除掩模结构和邻近掩模结构的预隔离层图案的侧壁上的部分形成开口和隔离层图案。 在形成隧道氧化物层之后，在隧道氧化物层和隔离层图案的侧壁上形成浮栅。

公开(公告)号：US06489252B2

公开(公告)日：2002-12-03

申请号：US09978650

申请日：2001-10-16

申请人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Jin-Gi Hong

发明人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Jin-Gi Hong

IPC分类号： H01L21469

CPC分类号： H01L21/02123 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/3125 ,  H01L21/316

摘要： A method of forming a SOG insulation layer of a semiconductor device comprises the steps of forming the SOG insulation layer on a substrate having a stepped pattern using a solution containing a polysilazane in an amount of less than 20% by weight in terms concentration of solid content, performing a pre-bake process for removing solvent ingredients in the insulation layer at a temperature of 50 to 350° C., and annealing at a temperature of 600 to 1200° C. The method of the invention further includes performing a hard bake process at a temperature of about 400° C. between the pre-bake process and the annealing step. Also, the polysilazane is desirably contained in an amount of 10 to 15% by weight.

公开(公告)号：US20050026443A1

公开(公告)日：2005-02-03

申请号：US10631848

申请日：2003-08-01

申请人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

发明人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02343 ,  H01L21/3125 ,  H01L21/3165 ,  H01L21/76229 ,  H01L21/76826 ,  H01L21/76828

摘要： A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

摘要翻译： 提供了一种通过将包含聚硅氮烷的SOG层施加到衬底然后使用氧化剂溶液将SOG层基本上转化为氧化硅层来在半导体器件加工期间形成氧化硅层的方法。 氧化剂溶液可以包括一种或多种氧化剂，包括例如臭氧，过氧化物，高锰酸盐，次氯酸盐，亚氯酸盐，氯酸盐，高氯酸盐，次溴酸盐，溴酸盐，溴酸盐，次碘酸盐，碘酸盐，碘酸盐和强酸。

公开(公告)号：US06645879B2

公开(公告)日：2003-11-11

申请号：US10215309

申请日：2002-08-08

申请人： Eun-Kee Hong ,  Ju-Bum Lee ,  Ju-Seon Goo ,  Myeong-Cheol Kim ,  Hong-Gun Kim

发明人： Eun-Kee Hong ,  Ju-Bum Lee ,  Ju-Seon Goo ,  Myeong-Cheol Kim ,  Hong-Gun Kim

IPC分类号： H01L2131

CPC分类号： H01L21/76897 ,  H01L21/31051 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76834 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/935 ,  H01L2924/00

摘要： Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device. Thus, a planar silicon oxide layer is formed between conductive patterns having a fine interval therebetween without creating a void. In addition, a metal layer pattern, which acts as a conductor in the conductive patterns, can be prevented from being oxidized when the silicon oxide layer is formed.

摘要翻译： 公开了用于形成能够在不导致工艺故障的细导电图案之间绝缘的半导体器件的氧化硅层的形成方法，以及用于形成具有氧化硅层的布线的方法。 在半导体衬底上形成导电图案之后，在导电图案和半导体衬底上依次形成抗氧化层。 抗氧化层防止氧化剂渗透到导电图案和半导体衬底中。 通过在抗氧化层上涂覆可回流氧化材料同时掩埋导电图案来形成可回流氧化物层。 通过热处理可回流氧化物层形成氧化硅层。 然后，在导电图案和暴露于半导体基板的抗氧化层之间填充的氧化硅层被蚀刻以形成接触孔，从而形成半导体器件的布线。 因此，在其间具有微细间隔的导电图案之间形成平面氧化硅层，而不产生空隙。 此外，当形成氧化硅层时，可以防止在导电图案中充当导体的金属层图案被氧化。

公开(公告)号：US20090012221A1

公开(公告)日：2009-01-08

申请号：US12194313

申请日：2008-08-19

申请人： Eunkee Hong ,  Kyu-Tae Na ,  Ju-Seon Goo ,  Hong-Gun Kim

发明人： Eunkee Hong ,  Kyu-Tae Na ,  Ju-Seon Goo ,  Hong-Gun Kim

IPC分类号： C08K5/06 ,  C08L83/08

CPC分类号： H01L21/3125 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/316 ,  H01L21/31695 ,  H01L21/76232 ,  H01L21/76837

摘要： A film is formed on a substrate including conductive patterns or trenches using a composition that included a solvent and perhydro-polysilazane having a weight average molecular weight of about 1,800 to 3,000 and a molecular weight distribution of more than about 2.2 to about 3.0. The film is changed into a silicon oxide film, and then an opening is formed through the silicon oxide film. A contact is formed in the opening by filling the opening with conductive material. The silicon oxide film of perhydro-polysilazane having low molecular weight becomes dense and uniform.

摘要翻译： 使用包含重量平均分子量约1,800至3,000且分子量分布大于约2.2至约3.0的溶剂和全氢化聚硅氮烷的组合物在包括导电图案或沟槽的基材上形成膜。 将膜变成氧化硅膜，然后通过氧化硅膜形成开口。 通过用导电材料填充开口在开口中形成接触。 具有低分子量的全氢聚硅氮烷的氧化硅膜变得致密且均匀。