公开(公告)号：US08963818B2

公开(公告)日：2015-02-24

申请号：US13212782

申请日：2011-08-18

Applicant: Chang-Sin Kim ,  Byeong-Doo Kang ,  Yong-Soon Lee ,  Ock-Jin Kim ,  Sang-Gon Lee

Inventor： Chang-Sin Kim ,  Byeong-Doo Kang ,  Yong-Soon Lee ,  Ock-Jin Kim ,  Sang-Gon Lee

IPC: G09G3/36 ,  G02F1/1343

CPC classification number: G09G3/3688 ,  G09G3/3648 ,  G09G2300/0413 ,  G09G2310/0232

Abstract: A display panel includes a plurality of data lines, a plurality of gate lines, a plurality of dummy loads, a pad portion and a fanout portion. The data lines are disposed in a display area, on which a plurality of pixels are disposed. The gate lines are disposed in the display area and cross the data lines. The dummy loads are disposed in a peripheral area surrounding the display area. The pad portion is disposed in the peripheral area and includes signal pads and dummy pads. The fanout portion includes a first fanout line portion connecting the data lines to the signal pads, and a second fanout line portion connecting the dummy loads to the dummy pads.

Abstract translation: 显示面板包括多条数据线，多条栅极线，多个虚拟负载，焊盘部分和扇出部分。 数据线设置在其上设置有多个像素的显示区域中。 栅极线设置在显示区域中并与数据线交叉。 虚拟负载设置在显示区域周围的周边区域中。 焊盘部分设置在周边区域中，并且包括信号焊盘和虚拟焊盘。 扇出部分包括将数据线连接到信号焊盘的第一扇出线部分和将虚拟负载连接到虚拟焊盘的第二扇出线部分。

公开(公告)号：US08730146B2

公开(公告)日：2014-05-20

申请号：US12539032

申请日：2009-08-11

Applicant: Yong-Soon Lee

Inventor： Yong-Soon Lee

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G2330/02

Abstract: A drive voltage generating circuit which has a first shifter receiving an input voltage and outputting a first drive voltage obtained by first shifting a voltage level of the input voltage; a second shifter receiving outputting the second drive voltage obtained by second shifting a voltage level of the first drive voltage; and a drive voltage controller adjusting one of a shifting amount of the first shifter and a shifting amount of the second shifter in accordance with a surrounding temperature, wherein the second drive voltage is continuously varied in an analog manner, in accordance with the surrounding temperature.

Abstract translation: 驱动电压产生电路，其具有接收输入电压的第一移位器，并输出通过首先移位输入电压的电压电平而获得的第一驱动电压; 接收第二移位器，接收输出通过第二移位第一驱动电压的电压电平而获得的第二驱动电压; 以及驱动电压控制器，其根据周围温度调整第一移位器的移位量和移位量中的一个，其中第二驱动电压根据周围温度以模拟方式连续变化。

公开(公告)号：US08558776B2

公开(公告)日：2013-10-15

申请号：US11999329

申请日：2007-12-04

Applicant: Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-Jin Jeon

Inventor： Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-Jin Jeon

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2320/0223

Abstract: In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Abstract translation: 在具有显示面板的显示面板和显示装置中，显示面板包括阵列和相对的基板。 阵列基板包括显示器和外围区域。 栅极和源极线形成在显示区域中。 在周边区域中形成栅极驱动部分和第一和第二时钟线。 栅极驱动部分将栅极信号输出到栅极线。 第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。 相对的衬底与阵列衬底组合并且包括公共电极层。 公共电极层具有图案化以暴露第一和第二时钟线的开口部分。 第一和第二时钟线的暴露部分具有基本上相同的面积。 因此，可以使门信号的延迟最小化并且可以防止门信号的失真。

公开(公告)号：US08179350B2

公开(公告)日：2012-05-15

申请号：US11222799

申请日：2005-09-12

Applicant: Haeng-Won Park ,  Seong-Young Lee ,  Yong-Soon Lee ,  Nam-Soo Kang ,  Seung-Hwan Moon ,  Bong-Jun Lee ,  Sung-Man Kim ,  Beom-Jun Kim ,  Yeon-Kyu Moon ,  Hyeong-Jun Park ,  Shin-Tack Kang

Inventor： Haeng-Won Park ,  Seong-Young Lee ,  Yong-Soon Lee ,  Nam-Soo Kang ,  Seung-Hwan Moon ,  Bong-Jun Lee ,  Sung-Man Kim ,  Beom-Jun Kim ,  Yeon-Kyu Moon ,  Hyeong-Jun Park ,  Shin-Tack Kang

IPC: G09G3/36 ,  G02F1/136

CPC classification number: G09G3/3648 ,  G02F1/1368 ,  G09G3/3614 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/0262

Abstract: A display device including a plurality of pixel electrodes arranged in a matrix including rows and columns and a plurality switching elements coupled with the pixel electrodes; a plurality of gate lines coupled with the switching elements and extending in a row direction, at least two gate lines assigned to a row; and a plurality of data lines coupled with the switching elements and extending in a column direction, a data line assigned to at least two columns, wherein each of the pixel electrodes has a first side and a second side that is farther from a data line than the first side, and the switching elements are disposed near the second sides of the pixel electrodes.

Abstract translation: 一种显示装置，包括：排列成包括行和列的矩阵的多个像素电极和与所述像素电极耦合的多个开关元件; 与开关元件耦合并沿行方向延伸的多条栅极线，分配给行的至少两条栅极线; 以及多个与所述开关元件耦合并沿列方向延伸的数据线，分配给至少两列的数据线，其中每个所述像素电极具有比数据线更远的第一侧和第二侧， 第一侧和开关元件设置在像素电极的第二侧附近。

公开(公告)号：US07692617B2

公开(公告)日：2010-04-06

申请号：US11111093

申请日：2005-04-20

Applicant: Dong-Gyu Kim ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Nam-Soo Kang ,  Haeng-Won Park

Inventor： Dong-Gyu Kim ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Nam-Soo Kang ,  Haeng-Won Park

IPC: G09G3/36

CPC classification number: G02F1/13454 ,  G02F1/1339 ,  G02F1/1345 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78669 ,  H01L29/78678

Abstract: Gate-driving circuitry of a thin film transistor array panel is formed on the same plane as a display area of the transistor array panel. The gate-driving circuitry includes driving circuitry and signal lines having apertures. Thus, a sufficient amount of light, even though illuminated from the thin film transistor array panel side, can reach a photosetting sealant overlapping at least in part the gate-driving circuitry. The thin film transistor array panel and the counter panel are put together air-tight and moisture-tight. Consequently, the gate-driving circuitry can avoid corrosion by moisture introduced from outside. Gate-driving circuitry malfunctions can also be reduced.

Abstract translation: 薄膜晶体管阵列面板的栅极驱动电路形成在与晶体管阵列面板的显示区域相同的平面上。 栅极驱动电路包括具有孔径的驱动电路和信号线。 因此，尽管从薄膜晶体管阵列面板侧照明，足够量的光可以到达与栅极驱动电路至少部分重叠的光固化密封剂。 将薄膜晶体管阵列面板和对面板放在一起，气密和防潮。 因此，栅极驱动电路可以避免从外部引入的湿气的腐蚀。 栅极驱动电路故障也可以减少。

公开(公告)号：US20080129717A1

公开(公告)日：2008-06-05

申请号：US11999329

申请日：2007-12-04

Applicant: Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-jin Jeon

Inventor： Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-jin Jeon

IPC: G06F3/038

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2320/0223

Abstract: In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Abstract translation: 在具有显示面板的显示面板和显示装置中，显示面板包括阵列和相对的基板。 阵列基板包括显示器和外围区域。 栅极和源极线形成在显示区域中。 在周边区域中形成栅极驱动部分和第一和第二时钟线。 栅极驱动部分将栅极信号输出到栅极线。 第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。 相对的衬底与阵列衬底组合并且包括公共电极层。 公共电极层具有图案化以暴露第一和第二时钟线的开口部分。 第一和第二时钟线的暴露部分具有基本上相同的面积。 因此，可以使门信号的延迟最小化并且可以防止门信号的失真。

公开(公告)号：US09672782B2

公开(公告)日：2017-06-06

申请号：US12949931

申请日：2010-11-19

Applicant: Jae-Hoon Lee ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Young-Su Kim ,  Chang-Ho Lee ,  Whee-Won Lee ,  Jun-Yong Song ,  Yu-Han Bae

Inventor： Jae-Hoon Lee ,  Seung-Hwan Moon ,  Yong-Soon Lee ,  Young-Su Kim ,  Chang-Ho Lee ,  Whee-Won Lee ,  Jun-Yong Song ,  Yu-Han Bae

IPC: G09G3/36 ,  G11C19/00 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/28

Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

公开(公告)号：US09659542B2

公开(公告)日：2017-05-23

申请号：US11230112

申请日：2005-09-19

Applicant: Haeng-Won Park ,  Seung-Hwan Moon ,  Nam-Soo Kang ,  Sung-Jae Moon ,  Sung-Man Kim ,  Seong-Young Lee ,  Yong-Soon Lee

Inventor： Haeng-Won Park ,  Seung-Hwan Moon ,  Nam-Soo Kang ,  Sung-Jae Moon ,  Sung-Man Kim ,  Seong-Young Lee ,  Yong-Soon Lee

IPC: G09G5/00 ,  G09G3/36 ,  G11C19/18

CPC classification number: G09G3/3677 ,  G09G2300/0426 ,  G11C19/184

Abstract: A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.

公开(公告)号：US20130055926A1

公开(公告)日：2013-03-07

申请号：US13697642

申请日：2010-07-09

Applicant: Yong-Soon Lee ,  Mu-Sik Noh

Inventor： Yong-Soon Lee ,  Mu-Sik Noh

IPC: C04B32/02

CPC classification number: C04B18/16 ,  B29B17/02 ,  B29B2017/0496 ,  B29K2105/16 ,  B29K2433/12 ,  B29K2995/002 ,  B29K2995/0021 ,  C04B18/20 ,  C04B20/02 ,  Y02W30/622 ,  Y02W30/625 ,  Y02W30/95 ,  Y02W30/96 ,  C04B20/026 ,  C04B2111/545

Abstract: Provided is a method of recycling waste scagliola, which includes a pre-treating step, a pyrolysing step, a resin recycling step, and a filler recycling step. The pre-treating step includes storing the waste scagliola of a dry dust type, drying and storing the waste scagliola of a wet dust type, or pulverizing and storing the waste scagliola of a scrap type. The pyrolysing step includes receiving and heating a recycling raw material stored in the dust or granular type in the pre-treating step, and decomposing the raw material into a resin mixed gas and a filler mixed solid material. The resin recycling step includes receiving the resin mixed gas decomposed in the pyrolysing step, and recycling a resin from which impurities are removed by a purifying process. The filler recycling step includes receiving the filler mixed solid material decomposed in the pyrolysing step, and recycling a filler from which impurities are removed by a firing process. Thereby, the resin and filler are more effectively recycled from the waste scagliola, so that it is possible to prevent environmental pollution caused by disposing the waste scagliola, and to enhance an effect of reducing resource waste according to resource recycling.

Abstract translation: 本发明提供了一种回收废弃锯齿刀的方法，其包括预处理步骤，热解步骤，树脂再循环步骤和填料再循环步骤。 预处理步骤包括储存干粉尘类型的废弃草皮，干燥并储存湿粉尘类型的废弃草皮，或粉碎和储存废料类型的废弃草药。 热解步骤包括在预处理步骤中接收和加热储存在粉尘或颗粒状的再循环原料，并将原料分解成树脂混合气体和填料混合固体材料。 树脂再循环步骤包括接收在热解步骤中分解的树脂混合气体，并通过净化处理循环除去杂质的树脂。 填料回收步骤包括接收在热解步骤中分解的填料混合固体材料，以及再循环通过焙烧过程除去杂质的填料。 由此，能够更有效地从废弃锯屑回收树脂和填料，从而可以防止由于处置废弃物而造成的环境污染，并且能够提高根据资源回收而减少资源浪费的效果。

公开(公告)号：US20100039364A1

公开(公告)日：2010-02-18

申请号：US12539032

申请日：2009-08-11

Applicant: Yong-Soon Lee

Inventor： Yong-Soon Lee

IPC: G09G3/36 ,  H03K3/00

CPC classification number: G09G3/3696 ,  G09G2330/02

Abstract: A drive voltage generating circuit which has a first shifter receiving an input voltage and outputting a first drive voltage obtained by first shifting a voltage level of the input voltage; a second shifter receiving outputting the second drive voltage obtained by second shifting a voltage level of the first drive voltage; and a drive voltage controller adjusting one of a shifting amount of the first shifter and a shifting amount of the second shifter in accordance with a surrounding temperature, wherein the second drive voltage is continuously varied in an analog manner, in accordance with the surrounding temperature.

Abstract translation: 驱动电压产生电路，其具有接收输入电压的第一移位器，并输出通过首先移位输入电压的电压电平而获得的第一驱动电压; 接收第二移位器，接收输出通过第二移位第一驱动电压的电压电平而获得的第二驱动电压; 以及驱动电压控制器，其根据周围温度调整第一移位器的移位量和移位量中的一个，其中第二驱动电压根据周围温度以模拟方式连续变化。