Layout verifying method for integrated circuit device
    2.
    发明授权
    Layout verifying method for integrated circuit device 失效
    集成电路器件布局验证方法

    公开(公告)号:US06539525B1

    公开(公告)日:2003-03-25

    申请号:US09680895

    申请日:2000-10-06

    Applicant: Yong-hun Kwon

    Inventor: Yong-hun Kwon

    CPC classification number: G06F17/5081

    Abstract: A method of verifying the layout of an integrated circuit device is provided. In a method of verifying the layout of an integrated circuit device having a memory block, a dummy circuit for receiving and outputting signals which are applied to the input and output ports included in the memory block, is inserted into the memory block. Then, the integrated circuit device is placed and routed using a computer. Next, a circuit-to-layout verification is performed with respect to the integrated circuit device, using a computer. Thus, the time for layout data verification with respect to the integrated circuit device is shortened and the verification made more accurate.

    Abstract translation: 提供一种验证集成电路器件布局的方法。 在验证具有存储块的集成电路装置的布局的方法中,将用于接收和输出施加到包括在存储块中的输入和输出端口的信号的虚拟电路插入到存储块中。 然后,使用计算机放置和布线集成电路装置。 接下来,使用计算机对集成电路装置执行电路对布局验证。 因此,相对于集成电路装置的布局数据验证的时间缩短,验证更准确。

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