公开(公告)号：US07172938B2

公开(公告)日：2007-02-06

申请号：US10987340

申请日：2004-11-12

申请人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim ,  Jae-Hwang Kim

发明人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim ,  Jae-Hwang Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.

摘要翻译： 隧道电介质层，电荷俘获层，第一长度限定层和第二长度限定层依次沉积在半导体衬底上。 这些层依次构图。 通过选择性侧蚀刻凹入第一长度限定层第一图案的两个侧壁。 在形成用于覆盖曝光的电荷俘获层的阻挡层和用于填充凹陷部分的栅极层之后，对栅极层进行图案化以形成间隔物形栅极。 用于源区和漏区的掺杂区形成在与栅极相邻的半导体衬底上。

公开(公告)号：US20050106816A1

公开(公告)日：2005-05-19

申请号：US10987340

申请日：2004-11-12

申请人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim ,  Jae-Hwang Kim

发明人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim ,  Jae-Hwang Kim

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.

摘要翻译： 隧道电介质层，电荷俘获层，第一长度限定层和第二长度限定层依次沉积在半导体衬底上。 这些层依次构图。 通过选择性侧蚀刻凹入第一长度限定层第一图案的两个侧壁。 在形成用于覆盖曝光的电荷俘获层的阻挡层和用于填充凹陷部分的栅极层之后，对栅极层进行图案化以形成间隔物形栅极。 用于源区和漏区的掺杂区形成在与栅极相邻的半导体衬底上。

公开(公告)号：US20060148172A1

公开(公告)日：2006-07-06

申请号：US11365147

申请日：2006-03-01

申请人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim

发明人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.

摘要翻译： 提供本地SONOS型存储器件及其制造方法。 该器件包括形成在硅衬底上的栅氧化层; 导电间隔物和虚拟间隔物，其形成在栅极氧化物层上并彼此分离，导电间隔物和虚设间隔物具有面向外的圆形表面; 形成在所述导电间隔物的侧壁上的一对绝缘间隔件和所述虚拟间隔件的彼此面对的侧壁; 在所述一对绝缘间隔物之间​​以自对准的方式形成的ONO层; 在所述一对绝缘间隔物之间​​以自对准的方式在所述ONO层上形成的导电层; 以及在导电间隔物外部的硅衬底和虚拟间隔物中形成的源极和漏极区。

公开(公告)号：US07256444B2

公开(公告)日：2007-08-14

申请号：US11365147

申请日：2006-03-01

申请人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim

发明人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.

摘要翻译： 提供本地SONOS型存储器件及其制造方法。 该器件包括形成在硅衬底上的栅氧化层; 导电间隔物和虚拟间隔物，其形成在栅极氧化物层上并彼此分离，导电间隔物和虚设间隔物具有面向外的圆形表面; 形成在所述导电间隔物的侧壁上的一对绝缘间隔件和所述虚拟间隔件的彼此面对的侧壁; 在所述一对绝缘间隔物之间​​以自对准的方式形成的ONO层; 在所述一对绝缘间隔物之间​​以自对准的方式在所述ONO层上形成的导电层; 以及在导电间隔物外部的硅衬底和虚拟间隔物中形成的源极和漏极区。

公开(公告)号：US20050054167A1

公开(公告)日：2005-03-10

申请号：US10888660

申请日：2004-07-09

申请人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim

发明人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.

摘要翻译： 提供本地SONOS型存储器件及其制造方法。 该器件包括形成在硅衬底上的栅氧化层; 导电间隔物和虚拟间隔物，其形成在栅极氧化物层上并彼此分离，导电间隔物和虚设间隔物具有面向外的圆形表面; 形成在所述导电间隔物的侧壁上的一对绝缘间隔件和所述虚拟间隔件的彼此面对的侧壁; 在所述一对绝缘间隔物之间​​以自对准的方式形成的ONO层; 在所述一对绝缘间隔物之间​​以自对准的方式在所述ONO层上形成的导电层; 以及在导电间隔物外部的硅衬底和虚拟间隔物中形成的源极和漏极区。

公开(公告)号：US07037781B2

公开(公告)日：2006-05-02

申请号：US10888660

申请日：2004-07-09

申请人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim

发明人： Yong-suk Choi ,  Seung-beom Yoon ,  Seong-gyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.

摘要翻译： 提供本地SONOS型存储器件及其制造方法。 该器件包括形成在硅衬底上的栅氧化层; 导电间隔物和虚拟间隔物，其形成在栅极氧化物层上并彼此分离，导电间隔物和虚设间隔物具有面向外的圆形表面; 形成在所述导电间隔物的侧壁上的一对绝缘间隔件和所述虚拟间隔件的彼此面对的侧壁; 在所述一对绝缘间隔物之间​​以自对准的方式形成的ONO层; 在所述一对绝缘间隔物之间​​以自对准的方式在所述ONO层上形成的导电层; 以及在导电间隔物外部的硅衬底和虚拟间隔物中形成的源极和漏极区。

公开(公告)号：US07029974B2

公开(公告)日：2006-04-18

申请号：US11083130

申请日：2005-03-17

申请人： Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

发明人： Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer. A split control gate is formed in the first opening, by etching the exposed control-gate conductive layer. The remaining mask layer pattern and inter-gate insulating layer are etched until the floating-gate conductive layer is exposed. The exposed floating-gate conductive layer is etched to form a split floating gate in the first opening.

摘要翻译： 提供一种分离栅极型非易失性半导体存储器件及其制造分离栅型非易失性半导体存储器件的方法。 在半导体衬底上形成栅绝缘层和浮栅导电层。 掩模层图案形成在浮栅导电层上以限定沿第一方向延伸的第一开口。 具有预定宽度的第一牺牲间隔物形成在对应于掩模层图案的两个侧壁上。 栅极间绝缘层形成在浮栅导电层上。 去除第一牺牲间隔物，并且蚀刻浮栅导电层，直到露出栅极绝缘层。 隧道绝缘层形成在浮栅导电层的露出部分上。 在半导体衬底的表面上形成控制栅导电层。 在控制栅极导电层上形成具有预定宽度的第二牺牲间隔物。 通过蚀刻暴露的控制栅极导电层，在第一开口中形成分裂控制栅极。 蚀刻剩余的掩模层图案和栅极间绝缘层，直到浮栅导电层露出。 蚀刻暴露的浮栅导电层，以在第一开口中形成分离浮栅。

公开(公告)号：US20060128098A1

公开(公告)日：2006-06-15

申请号：US11349402

申请日：2006-02-07

申请人： Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

发明人： Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer. A split control gate is formed in the first opening, by etching the exposed control-gate conductive layer. The remaining mask layer pattern and inter-gate insulating layer are etched until the floating-gate conductive layer is exposed. The exposed floating-gate conductive layer is etched to form a split floating gate in the first opening.

公开(公告)号：US07256448B2

公开(公告)日：2007-08-14

申请号：US11349402

申请日：2006-02-07

申请人： Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

发明人： Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer. A split control gate is formed in the first opening, by etching the exposed control-gate conductive layer. The remaining mask layer pattern and inter-gate insulating layer are etched until the floating-gate conductive layer is exposed. The exposed floating-gate conductive layer is etched to form a split floating gate in the first opening.

摘要翻译： 提供一种分离栅极型非易失性半导体存储器件及其制造分离栅型非易失性半导体存储器件的方法。 在半导体衬底上形成栅绝缘层和浮栅导电层。 掩模层图案形成在浮栅导电层上以限定沿第一方向延伸的第一开口。 具有预定宽度的第一牺牲间隔物形成在对应于掩模层图案的两个侧壁上。 栅极间绝缘层形成在浮栅导电层上。 去除第一牺牲间隔物，并且蚀刻浮栅导电层，直到露出栅极绝缘层。 隧道绝缘层形成在浮栅导电层的露出部分上。 在半导体衬底的表面上形成控制栅导电层。 在控制栅极导电层上形成具有预定宽度的第二牺牲间隔物。 通过蚀刻暴露的控制栅极导电层，在第一开口中形成分裂控制栅极。 蚀刻剩余的掩模层图案和栅极间绝缘层，直到浮栅导电层露出。 蚀刻暴露的浮栅导电层，以在第一开口中形成分离浮栅。

公开(公告)号：US20050208744A1

公开(公告)日：2005-09-22

申请号：US11083130

申请日：2005-03-17

申请人： Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

发明人： Heeseog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim ,  Yong-suk Choi

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer. A split control gate is formed in the first opening, by etching the exposed control-gate conductive layer. The remaining mask layer pattern and inter-gate insulating layer are etched until the floating-gate conductive layer is exposed. The exposed floating-gate conductive layer is etched to form a split floating gate in the first opening.

摘要翻译： 提供一种分离栅极型非易失性半导体存储器件及其制造分离栅型非易失性半导体存储器件的方法。 在半导体衬底上形成栅绝缘层和浮栅导电层。 掩模层图案形成在浮栅导电层上以限定沿第一方向延伸的第一开口。 具有预定宽度的第一牺牲间隔物形成在对应于掩模层图案的两个侧壁上。 栅极间绝缘层形成在浮栅导电层上。 去除第一牺牲间隔物，并且蚀刻浮栅导电层，直到露出栅极绝缘层。 隧道绝缘层形成在浮栅导电层的露出部分上。 在半导体衬底的表面上形成控制栅导电层。 在控制栅极导电层上形成具有预定宽度的第二牺牲间隔物。 通过蚀刻暴露的控制栅极导电层，在第一开口中形成分裂控制栅极。 蚀刻剩余的掩模层图案和栅极间绝缘层，直到浮栅导电层露出。 蚀刻暴露的浮栅导电层，以在第一开口中形成分离浮栅。