公开(公告)号：US20120238082A1

公开(公告)日：2012-09-20

申请号：US13477239

申请日：2012-05-22

申请人： Yongxun LIU ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

发明人： Yongxun LIU ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

IPC分类号： H01L21/20 ,  B82Y40/00

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/775

摘要： A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.

摘要翻译： 一种纳米线场效应晶体管的制造方法，包括制备具有（100）表面取向的SOI衬底的步骤; 将包括SOI衬底的硅晶体层加工成具有矩形横截面的立式板状构件; 通过取向依赖的湿式蚀刻和热氧化将硅晶体层加工成两个三角柱状部件彼此之间彼此间隔开的形状，以便沿三角形柱状部件的棱线面对; 并通过氢退火或热氧化将两个三角形柱状构件加工成构成纳米线的圆形柱状构件。

公开(公告)号：US20110057163A1

公开(公告)日：2011-03-10

申请号：US12991226

申请日：2009-06-05

申请人： Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

发明人： Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L29/775 ,  B82Y99/00

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/775

摘要： Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing a nano-wire field effect transistor including two columnar members made of a silicon crystal configuring a nano-wire on a substrate are arranged on a substrate in parallel and one above the other, and an SOI substrate having a (100) surface orientation; processing a silicon crystal layer configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other as to face along the ridge lines of the triangular columnar members; and processing the triangular columnar member into a circular columnar member configuring a nano-wire by hydrogen-annealing or a thermal oxidation; and an integrated circuit including the transistor.

摘要翻译： 提供一种制造纳米线场效应晶体管的方法，包括以下步骤：制备纳米线场效应晶体管，其纳米线场效应晶体管包括两个由在基板上构成纳米线的硅晶体制成的柱状部件并联在基板上， 并且具有（100）表面取向的SOI衬底; 将构成SOI衬底的硅晶层加工成具有矩形横截面的立板形构件; 通过取向依赖的湿蚀刻和热氧化将硅晶体加工成两个三角柱状部件彼此之间彼此间隔开地沿着三角形柱状部件的棱线彼此间隔地布置的形状; 并通过氢退火或热氧化将三角柱状构件加工成构成纳米线的圆柱形构件; 以及包括晶体管的集成电路。

公开(公告)号：US08399330B2

公开(公告)日：2013-03-19

申请号：US13477239

申请日：2012-05-22

申请人： Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

发明人： Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

IPC分类号： H01L21/331

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/775

摘要： A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation.

摘要翻译： 一种纳米线场效应晶体管的制造方法，包括以下步骤：制备具有（100）表面取向的SOI衬底; 将包括SOI衬底的硅晶体层加工成具有矩形横截面的立式板状构件; 通过取向依赖的湿式蚀刻和热氧化将硅晶体层加工成两个三角柱状部件彼此之间彼此间隔开的形状，以便沿三角形柱状部件的棱线面对; 并通过氢退火或热氧化将两个三角形柱状构件加工成构成纳米线的圆形柱状构件。

公开(公告)号：US20110073842A1

公开(公告)日：2011-03-31

申请号：US12993880

申请日：2009-06-05

申请人： Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

发明人： Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

IPC分类号： H01L29/786 ,  H01L21/84 ,  B82Y99/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

摘要： Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.

摘要翻译： 提供一种制造纳米线场效应晶体管的方法，包括以下步骤：制备具有（100）表面取向的SOI衬底和纳米线场效应晶体管，其中构成纳米线的两个三角柱形构件由 在具有（100）表面的SOI衬底上，使三角柱状构件的棱线经由绝缘体面对，从而将硅晶体层彼此重叠地布置; 将构成SOI衬底的硅晶体加工成具有矩形横截面的立式板状构件; 并且作为纳米线，通过取向相关的湿法蚀刻将硅晶体加工成两个三角柱形部件一个在另一个上方布置的形状，使得构成纳米线的三角柱形部件的脊线面向通过脊 线，以及包括纳米线场效应晶体管的集成电路。

公开(公告)号：US08399879B2

公开(公告)日：2013-03-19

申请号：US12993880

申请日：2009-06-05

申请人： Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

发明人： Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/019 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

摘要： Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.

摘要翻译： 提供一种制造纳米线场效应晶体管的方法，包括以下步骤：制备具有（100）表面取向的SOI衬底和纳米线场效应晶体管，其中构成纳米线的两个三角柱形构件由 在具有（100）表面的SOI衬底上，使三角柱状构件的棱线经由绝缘体面对，从而将硅晶体层彼此重叠地布置; 将构成SOI衬底的硅晶体加工成具有矩形横截面的立式板状构件; 并且作为纳米线，通过取向相关的湿法蚀刻将硅晶体加工成两个三角柱形部件一个在另一个上方布置的形状，使得构成纳米线的三角柱形部件的脊线面向通过脊 线，以及包括纳米线场效应晶体管的集成电路。

公开(公告)号：US07999321B2

公开(公告)日：2011-08-16

申请号：US12602314

申请日：2008-05-09

申请人： Yongxun Liu ,  Takashi Matsukawa ,  Meishoku Masahara ,  Kazuhiko Endo ,  Shinichi Ouchi

发明人： Yongxun Liu ,  Takashi Matsukawa ,  Meishoku Masahara ,  Kazuhiko Endo ,  Shinichi Ouchi

IPC分类号： H01L27/12

CPC分类号： H01L29/78609 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： A field-effect transistor comprising a movable gate electrode that suppresses a leakage current from the gate electrode, and has a large current drivability and a low leakage current between a source and a drain. The field-effect transistor comprises: an insulating substrate; a semiconductor layer of triangle cross-sectional shape formed on the insulating substrate, having a gate insulation film on a surface, and forming a channel in a lateral direction; fixed electrodes that are arranged adjacent to both sides of the semiconductor layer and in parallel to the semiconductor layer, each of the electrodes having an insulation film on a surface; a source/drain formed at the end part of the semiconductor layer; and the movable gate electrode formed above the semiconductor layer and the fixed electrodes with a gap.

摘要翻译： 一种场效应晶体管，包括抑制来自栅电极的漏电流的可移动栅电极，并且在源极和漏极之间具有大的电流驱动能力和低的漏电流。 场效应晶体管包括：绝缘基板; 形成在所述绝缘基板上的三角形截面形状的半导体层，在表面上具有栅极绝缘膜，并且沿横向形成沟道; 固定电极，其布置成与半导体层的两侧相邻并且平行于半导体层，每个电极在表面上具有绝缘膜; 在半导体层的端部形成的源极/漏极; 以及形成在半导体层上方的可动栅电极和具有间隙的固定电极。

公开(公告)号：US08077510B2

公开(公告)日：2011-12-13

申请号：US12517696

申请日：2007-12-06

申请人： Shinichi Ouchi ,  Yongxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

发明人： Shinichi Ouchi ,  Yongxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

IPC分类号： G11C11/34 ,  G11C11/00

CPC分类号： H01L27/1203 ,  G11C11/412 ,  G11C11/413 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/785

摘要： An SRAM device including a memory cell, the memory cell having two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, a first bias voltage is applied to bias voltage input gates of the transistors of the memory cells in a row including a memory cell being accessed for reading or writing, and a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation.

摘要翻译： 一种包括存储单元的SRAM器件，具有连接到字线的两个存取晶体管的存储单元以及具有互补晶体管的触发器电路，该晶体管是具有立方半导体薄板的场效应晶体管，逻辑信号输入栅极 以及偏置电压输入栅极，所述栅极夹着半导体薄板并彼此电分离，将第一偏置电压施加到存储器单元的晶体管的偏置电压输入栅极，所述存储器单元的晶体管包括被访问的存储器单元 读取或写入，并且第二偏置电压被施加到包括存储器保持操作下的存储器单元的行中的存储器单元的晶体管的偏置电压输入栅极。

公开(公告)号：US20100315861A1

公开(公告)日：2010-12-16

申请号：US12521408

申请日：2007-12-20

申请人： Shinichi Ouchi ,  Yongxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

发明人： Shinichi Ouchi ,  Yongxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

IPC分类号： G11C11/00

CPC分类号： H01L27/1104 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/785 ,  H01L29/7856

摘要： In an SRAM cell including a first to a fourth semiconductor thin plates which stand on a substrate and are arranged in parallel to each other, on each of the four semiconductor thin plates being formed a first four-terminal double-gate FET with a first conductivity type; a second and a third four-terminal double-gate FETs which are connected in series with each other and have a second conductivity type; a fourth and a fifth four-terminal double-gate FETs which are connected in series with each other and have the second conductivity type; a sixth four-terminal double-gate FET with the first conductivity type, wherein the third and the fourth four-terminal double-gate FETs form select transistors, and the first, the second, the fifth and the sixth four-terminal double-gate FETs form a CMOS inverter, logic signal input gates of the first and the sixth four-terminal double-gate FETs are arranged on the side facing the second and the third semiconductor thin plates, respectively, while threshold voltage control gates of the second to the fifth four-terminal double-gate FETs are arranged on the sides facing each other and are commonly connected to a first bias line. Threshold voltage control gates of the first and the sixth four-terminal double-gate FETs are commonly connected to a second bias line. A word line, the first bias line and the second bias line are arranged orthogonally to the direction of arrangement of the first to the fourth semiconductor thin plates.

摘要翻译： 在包括站立在基板上并彼此平行布置的第一至第四半导体薄板的SRAM单元中，在四个半导体薄板中的每一个上形成具有第一导电性的第一四端子双栅极FET 类型; 第二和第三四端子双栅极FET，它们彼此串联并具有第二导电类型; 第四和第五四端子双栅极FET，它们彼此串联并具有第二导电类型; 具有第一导电类型的第六个四端子双栅极FET，其中第三和第四四端子双栅极FET形成选择晶体管，并且第一，第二，第五和第六四端子双栅极 FET形成CMOS反相器，第一和第六四端子双栅极FET的逻辑信号输入栅极分别布置在面向第二和第三半导体薄板的一侧，而第二至第四半导体FET的阈值电压控制栅极 第五四端子双栅FET被布置在彼此面对的侧面上，并且共同连接到第一偏置线。 第一和第六四端子双栅极FET的阈值电压控制栅极共同连接到第二偏置线。 字线，第一偏置线和第二偏置线与第一至第四半导体薄板的排列方向垂直。

公开(公告)号：US20100213546A1

公开(公告)日：2010-08-26

申请号：US12602314

申请日：2008-05-09

申请人： Yongxun Liu ,  Takashi Matsukawa ,  Meishoku Masahara ,  Kazuhiko Endo ,  Shinichi Ouchi

发明人： Yongxun Liu ,  Takashi Matsukawa ,  Meishoku Masahara ,  Kazuhiko Endo ,  Shinichi Ouchi

IPC分类号： H01L27/12

CPC分类号： H01L29/78609 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： A field-effect transistor comprising a movable gate electrode that suppresses a leakage current from the gate electrode, and has a large current drivability and a low leakage current between a source and a drain. The field-effect transistor comprises: an insulating substrate; a semiconductor layer of triangle cross-sectional shape formed on the insulating substrate, having a gate insulation film on a surface, and forming a channel in a lateral direction; fixed electrodes that are arranged adjacent to both sides of the semiconductor layer and in parallel to the semiconductor layer, each of the electrodes having an insulation film on a surface; a source/drain formed at the end part of the semiconductor layer; and the movable gate electrode formed above the semiconductor layer and the fixed electrodes with a gap.

摘要翻译： 一种场效应晶体管，包括抑制来自栅电极的漏电流的可移动栅电极，并且在源极和漏极之间具有大的电流驱动能力和低的漏电流。 场效应晶体管包括：绝缘基板; 形成在所述绝缘基板上的三角形截面形状的半导体层，在表面上具有栅极绝缘膜，并且沿横向形成沟道; 固定电极，其布置成与半导体层的两侧相邻并且平行于半导体层，每个电极在表面上具有绝缘膜; 源极/漏极，形成在半导体层的端部; 以及形成在半导体层上方的可动栅电极和具有间隙的固定电极。

公开(公告)号：US08040717B2

公开(公告)日：2011-10-18

申请号：US12521408

申请日：2007-12-20

申请人： Shinichi Ouchi ,  Yongxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

发明人： Shinichi Ouchi ,  Yongxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

IPC分类号： G11C11/00

CPC分类号： H01L27/1104 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/785 ,  H01L29/7856

摘要： A static random access memory (SRAM) cell includes a first to a fourth semiconductor thin plate that are provided on a substrate and are arranged parallel to each other. On respective semiconductor thin plates, there is formed a first four-terminal double-gate field effect transistor (FET) with a first conductivity type, a second and a third four-terminal double-gate FET which are connected in series with each other and have a second conductivity type, a fourth and a fifth four-terminal double-gate FET which are connected in series with each other and have the second conductivity type, and a sixth four-terminal double-gate FET with the first conductivity type. The third and the fourth four-terminal double-gate FETs form select transistors, and the first, second, fifth and sixth four-terminal double-gate FETs form a complementary metal-oxide-semiconductor (CMOS) inverter.

摘要翻译： 静态随机存取存储器（SRAM）单元包括设置在基板上并且彼此平行布置的第一至第四半导体薄板。 在相应的半导体薄板上形成具有第一导电类型的第一四端双栅场效应晶体管（FET），彼此串联连接的第二和第三四端双栅FET 具有彼此串联并具有第二导电类型的第二导电类型，第四和第五四端子双栅极FET以及具有第一导电类型的第六四端子双栅极FET。 第三和第四四端子双栅极FET形成选择晶体管，第一，第二，第五和第六四端子双栅极FET形成互补的金属氧化物半导体（CMOS）反相器。