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公开(公告)号：US20080230804A1
公开(公告)日：2008-09-25
申请号：US12036703
申请日：2008-02-25
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/872 , H01L21/283
CPC分类号： H01L29/47 , H01L21/28518 , H01L21/76814 , H01L21/823814 , H01L21/823835 , H01L29/475
摘要： A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.
摘要翻译： 公开了一种半导体器件，其具有即使电子或空穴为多数载流子的具有降低的电接触电阻的电极。 该器件在半导体衬底的顶表面中具有n型扩散层和p型扩散层。 该装置还具有图案化的第一和第二金属线分别覆盖在n型和p型扩散层之间，介于其间的介电层，用于在n型扩散层和第一金属之间电连接的第一接触电极 电线和用于在p型扩散层和第二金属线之间连接的第二接触电极。 与n型扩散层接触的第一接触电极部分和与p型扩散层接触的第二接触电极部分分别由包含金属的第一导体和含有稀土金属的第二导体形成。
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公开(公告)号：US07642604B2
公开(公告)日：2010-01-05
申请号：US12036703
申请日：2008-02-25
IPC分类号： H01L23/48
CPC分类号： H01L29/47 , H01L21/28518 , H01L21/76814 , H01L21/823814 , H01L21/823835 , H01L29/475
摘要： A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.
摘要翻译： 公开了一种半导体器件，其具有即使电子或空穴为多数载流子的具有降低的电接触电阻的电极。 该器件在半导体衬底的顶表面中具有n型扩散层和p型扩散层。 该装置还具有图案化的第一和第二金属线分别覆盖在n型和p型扩散层之间，介于其间的介电层，用于在n型扩散层和第一金属之间电连接的第一接触电极 电线和用于在p型扩散层和第二金属线之间连接的第二接触电极。 与n型扩散层接触的第一接触电极部分和与p型扩散层接触的第二接触电极部分分别由包含金属的第一导体和含有稀土金属的第二导体形成。
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3.发明申请公开(公告)号：US20090152652A1
公开(公告)日：2009-06-18
申请号：US12323770
申请日：2008-11-26
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4975 , H01L21/26506 , H01L21/28097 , H01L21/28518 , H01L21/28537 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L23/485 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.
摘要翻译： 这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。 在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。 第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。 将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。 第二金属沉积在金属半导体化合物层上。 通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。
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4.发明申请公开(公告)号：US20090008726A1
公开(公告)日：2009-01-08
申请号：US12051947
申请日：2008-03-20
申请人： Takashi Yamauchi , Yoshifumi Nishi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato
发明人： Takashi Yamauchi , Yoshifumi Nishi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato
IPC分类号： H01L47/00 , H01L21/425
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823821 , H01L21/823835 , H01L21/823842 , H01L29/785
摘要： A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer.
摘要翻译： 提供了制造半导体器件降低n型和p型MISFET的界面电阻的方法。 根据该方法，在第一半导体区域上形成栅极电介质膜和n型MISFET的栅电极，在第二半导体区域上形成p型MISFET的栅极电介质膜和栅电极， 通过将As离子注入第一半导体区域形成n型扩散层，在n型扩散层上沉积含有Ni的第一金属之后，通过第一热处理形成第一硅化物层，制作第一硅化物层 在第一硅化物层和第二半导体区域上沉积含有Ni的第二金属沉积第二热处理之后，在形成第二硅化物层和在第二硅化物层中离子注入B或Mg之后提供第三热处理。
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公开(公告)号：US07977182B2
公开(公告)日：2011-07-12
申请号：US12323770
申请日：2008-11-26
IPC分类号： H01L21/8238 , H01L29/04 , H01L29/10 , H01L31/036 , H01L21/285
CPC分类号： H01L29/4975 , H01L21/26506 , H01L21/28097 , H01L21/28518 , H01L21/28537 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L23/485 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.
摘要翻译： 这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。 在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。 第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。 将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。 第二金属沉积在金属半导体化合物层上。 通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。
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公开(公告)号：US20080179752A1
公开(公告)日：2008-07-31
申请号：US11898295
申请日：2007-09-11
IPC分类号： H01L29/78 , H01L21/336 , H01L23/48
CPC分类号： H01L29/66795 , H01L21/26513 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/47 , H01L29/66507 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66643 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.
摘要翻译： 公开了具有应变通道区域的金属绝缘体半导体场效应晶体管（MISFET）。 还公开了一种制造具有低电阻结界面的半导体器件的方法。 该制造方法包括在硅衬底上形成栅电极的步骤，其间夹有栅绝缘膜。 然后，在栅极两侧的衬底表面中或其上形成一对重掺杂的p（p + SUP +）型扩散层，使其浓度达到5×10 19 原子/ cm 3以上且小于或等于1×10 21原子/ cm 3。 接下来，在各层施加压缩应变的状态下，通过与金属反应来硅化p + + +层。
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7.发明授权Method of forming a silicide layer while applying a compressive or tensile strain to impurity layers 失效在对杂质层施加压缩或拉伸应变的同时形成硅化物层的方法公开(公告)号：US07807538B2
公开(公告)日：2010-10-05
申请号：US11898295
申请日：2007-09-11
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/26513 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/47 , H01L29/66507 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66643 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.
摘要翻译： 公开了具有应变通道区域的金属绝缘体半导体场效应晶体管（MISFET）。 还公开了一种制造具有低电阻结界面的半导体器件的方法。 该制造方法包括在硅衬底上形成栅电极的步骤，其间夹有栅绝缘膜。 然后，在栅电极两侧的基板表面中或其上形成一对重掺杂的p（p +）型扩散层，其浓度为5×1019原子/ cm3以上且小于等于1× 1021原子/ cm3。 接下来，在各层施加压缩应变的状态下，通过与金属反应来硅化p +型层。
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公开(公告)号：US07456096B2
公开(公告)日：2008-11-25
申请号：US11530724
申请日：2006-09-11
申请人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
发明人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
IPC分类号： H01L29/45
CPC分类号： H01L21/28537 , H01L21/265 , H01L21/28052 , H01L21/28518 , H01L29/41791 , H01L29/66143 , H01L29/66643 , H01L29/66795 , H01L29/7833 , H01L29/7839 , H01L29/785 , H01L29/872 , H01L2029/7858
摘要： It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.
摘要翻译： 可以降低硅化镍膜与硅之间界面处的界面电阻。 半导体制造方法包括：在硅衬底上形成杂质区域，杂质被引入杂质区域; 沉积Ni层以覆盖杂质区域; 通过退火将杂质区的表面改变成NiSi 2层; 在NiSi 2层上形成Ni层; 并通过退火对NiSi 2层进行硅化。
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公开(公告)号：US07902612B2
公开(公告)日：2011-03-08
申请号：US12208730
申请日：2008-09-11
申请人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
发明人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
IPC分类号： H01L29/76
CPC分类号： H01L21/28537 , H01L21/265 , H01L21/28052 , H01L21/28518 , H01L29/41791 , H01L29/66143 , H01L29/66643 , H01L29/66795 , H01L29/7833 , H01L29/7839 , H01L29/785 , H01L29/872 , H01L2029/7858
摘要： It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.
摘要翻译： 可以降低硅化镍膜与硅之间界面处的界面电阻。 半导体制造方法包括：在硅衬底上形成杂质区域，杂质被引入杂质区域; 沉积Ni层以覆盖杂质区域; 通过退火将杂质区的表面改变为NiSi2层; 在NiSi2层上形成Ni层; 并通过退火将NiSi2层硅化。
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公开(公告)号：US20070141836A1
公开(公告)日：2007-06-21
申请号：US11530724
申请日：2006-09-11
申请人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
发明人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
IPC分类号： H01L21/4763
CPC分类号： H01L21/28537 , H01L21/265 , H01L21/28052 , H01L21/28518 , H01L29/41791 , H01L29/66143 , H01L29/66643 , H01L29/66795 , H01L29/7833 , H01L29/7839 , H01L29/785 , H01L29/872 , H01L2029/7858
摘要： It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.
摘要翻译： 可以降低硅化镍膜与硅之间界面处的界面电阻。 半导体制造方法包括：在硅衬底上形成杂质区域，杂质被引入杂质区域; 沉积Ni层以覆盖杂质区域; 通过退火将杂质区的表面改变成NiSi 2层; 在NiSi 2层上形成Ni层; 并通过退火对NiSi 2层进行硅化。
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