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公开(公告)号：US20070200138A1
公开(公告)日：2007-08-30
申请号：US11709272
申请日：2007-02-22
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L29/74
CPC分类号： H01L27/0611 , H01L29/7395 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.
摘要翻译： 半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。 第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。
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公开(公告)号：US20060244053A1
公开(公告)日：2006-11-02
申请号：US11398551
申请日：2006-04-06
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/1095 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a fourth semiconductor layer in a part of the third semiconductor layer; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer; a gate insulation film on an inner wall of the trench; a gate electrode on the gate insulation film in the trench; a first electrode; and a second electrode. The trench includes a bottom with a curved surface having a curvature radius equal to or smaller than 0.5 μm.
摘要翻译： 一种半导体器件包括：第一半导体层; 在所述第一半导体层上的第二半导体层; 第二半导体层上的第三半导体层; 在所述第三半导体层的一部分中的第四半导体层; 穿过第四半导体层和第三半导体层并到达第二半导体层的沟槽; 沟槽内壁上的栅极绝缘膜; 在沟槽中的栅极绝缘膜上的栅电极; 第一电极; 和第二电极。 沟槽包括具有曲率半径等于或小于0.5μm的曲面的底部。
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公开(公告)号：US07667269B2
公开(公告)日：2010-02-23
申请号：US11398551
申请日：2006-04-06
IPC分类号： H01L23/62
CPC分类号： H01L29/7397 , H01L29/1095 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a fourth semiconductor layer in a part of the third semiconductor layer; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer; a gate insulation film on an inner wall of the trench; a gate electrode on the gate insulation film in the trench; a first electrode; and a second electrode. The trench includes a bottom with a curved surface having a curvature radius equal to or smaller than 0.5 μm.
摘要翻译： 一种半导体器件包括：第一半导体层; 在所述第一半导体层上的第二半导体层; 第二半导体层上的第三半导体层; 在所述第三半导体层的一部分中的第四半导体层; 穿过第四半导体层和第三半导体层并到达第二半导体层的沟槽; 沟槽内壁上的栅极绝缘膜; 在沟槽中的栅极绝缘膜上的栅电极; 第一电极; 和第二电极。 沟槽包括具有曲率半径等于或小于0.5μm的曲面的底部。
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公开(公告)号：US07456484B2
公开(公告)日：2008-11-25
申请号：US11648894
申请日：2007-01-03
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L21/00
CPC分类号： H01L29/7395 , H01L27/0664 , H01L29/0834 , H01L29/66333 , H01L29/861
摘要： A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.
摘要翻译： 半导体器件包括：具有第一和第二半导体层的半导体衬底; IGBT，其具有集电极区域，第一半导体层中的基极区域，基极区域中的发射极区域和发射极区域与第一半导体层之间的基极区域中的沟道区域; 在所述第一半导体层中具有阳极区域的二极管和所述第一半导体层上的阴极电极; 和电阻区域。 集电极区域和第二半导体层设置在第一半导体层上。 用于增加第二半导体层的电阻的电阻区域通过绕过集电极区域而被布置在通过第一半导体层和第二半导体层的沟道区域和阴极电极之间的电流通路中。
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公开(公告)号：US20070158680A1
公开(公告)日：2007-07-12
申请号：US11648894
申请日：2007-01-03
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L29/74
CPC分类号： H01L29/7395 , H01L27/0664 , H01L29/0834 , H01L29/66333 , H01L29/861
摘要： A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.
摘要翻译： 半导体器件包括：具有第一和第二半导体层的半导体衬底; IGBT，其具有集电极区域，第一半导体层中的基极区域，基极区域中的发射极区域和发射极区域与第一半导体层之间的基极区域中的沟道区域; 在所述第一半导体层中具有阳极区域和在所述第一半导体层上的阴极电极的二极管; 和电阻区域。 集电极区域和第二半导体层设置在第一半导体层上。 用于增加第二半导体层的电阻的电阻区域通过绕过集电极区域而被布置在通过第一半导体层和第二半导体层的沟道区域和阴极电极之间的电流通路中。
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公开(公告)号：US08102025B2
公开(公告)日：2012-01-24
申请号：US11709272
申请日：2007-02-22
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L29/66
CPC分类号： H01L27/0611 , H01L29/7395 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.
摘要翻译： 半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。 第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。
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公开(公告)号：US06603173B1
公开(公告)日：2003-08-05
申请号：US09391236
申请日：1999-09-07
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/4236
摘要： A vertical power MOSFET, which can improve a surge withstand voltage and a surge withstand voltage against a surge voltage from an inductance load L. The vertical power MOSFET has a plurality of unit cells. The unit cell is formed from a MOSFET that uses a p-type base layer at a sidewall of a rectangular U-groove as a channel portion. Each of the p-type base layer of each unit cell is connected each others Accordingly, it can restrain an impurity concentration of a corner portion (a portion positioned at a corner) of the rectangular p-type base layer from being decreased. Therefore, it can reduce the difference in distance from the end portion of the p-type base layer to the end portion of the depletion layer. As a result, it can improve the surge withstand voltage when a surge voltage is input from an inductance load L.
摘要翻译： 一种垂直功率MOSFET，其可以提高抗电压耐受电压和抵抗来自电感负载L的浪涌电压的浪涌耐受电压。垂直功率MOSFET具有多个单元电池。 单位电池由在矩形U形槽的侧壁处使用p型基底层作为沟道部分的MOSFET形成。 每个单电池的p型基极层彼此连接。因此，能够抑制矩形p型基极层的角部（位于角部的部分）的杂质浓度降低。 因此，可以减少与p型基底层的端部到耗尽层的端部的距离的差异。 因此，当从电感负载L输入浪涌电压时，可以提高浪涌耐受电压。
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8.发明授权公开(公告)号：US06765266B2
公开(公告)日：2004-07-20
申请号：US10308085
申请日：2002-12-03
IPC分类号： H01L2360
CPC分类号： H01L29/404 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings adjacent the first plate ring. Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding the surge voltage increases.
摘要翻译： 在本发明的半导体器件中，形成第一半导体区域，使得其周缘位于与位于其最内侧的场板环之一相对应的第一场板环与第二场板环之间， 对应于邻近第一板环的场板环中的一个。 因此，当对本发明的半导体器件施加浪涌电压时，位于第一场的场板环之下的隔离膜的一部分处的电场浓度被放宽，并且电场强度降低。 因此，用于耐受浪涌电压的隔离膜的可靠性增加。
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公开(公告)号：US20070215898A1
公开(公告)日：2007-09-20
申请号：US11714201
申请日：2007-03-06
申请人： Yoshihiko Ozeki , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Yukio Tsuzuki
IPC分类号： H01L29/74
CPC分类号： H01L29/0619 , H01L29/7397
摘要： A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. Abase region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is formed on the first surface around the IGBT, and a carrier collecting region is formed in the vicinity of the region having the low breakdown voltage. The IGBT is prevented from being broken down due to an avalanche phenomenon, because the breakdown occurs in the region having the low breakdown voltage, and carriers of the breakdown current are collected through the carrier collecting region. The breakdown of the IGBT is further effectively prevented by forming a guard ring for suppressing electric field concentration around the region having the low breakdown voltage.
摘要翻译： 在半导体衬底上形成具有绝缘栅双极晶体管（IGBT）的半导体器件。 在衬底的第一表面上形成有发光二极管和发射极，同时在衬底的第二表面上形成集电极层。 在IGBT周围的第一表面上形成具有低击穿电压的区域，并且在具有低击穿电压的区域附近形成载流子收集区域。 由于在具有低击穿电压的区域中发生击穿，因此防止IGBT由于雪崩现象而分解，并且通过载流子收集区域收集击穿电流的载流子。 通过形成用于抑制具有低击穿电压的区域周围的电场浓度的保护环，进一步有效地防止了IGBT的击穿。
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公开(公告)号：US07692221B2
公开(公告)日：2010-04-06
申请号：US11714201
申请日：2007-03-06
申请人： Yoshihiko Ozeki , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Yukio Tsuzuki
IPC分类号： H01L27/088
CPC分类号： H01L29/0619 , H01L29/7397
摘要： A semiconductor device having an insulated gate bipolar transistor (IGBT) is formed on a semiconductor substrate. A base region and an emitter are formed on a first surface of the substrate while a collector layer is formed on second surface of the substrate. A region having a low breakdown voltage is formed on the first surface around the IGBT, and a carrier collecting region is formed in the vicinity of the region having the low breakdown voltage. The IGBT is prevented from being broken down due to an avalanche phenomenon, because the breakdown occurs in the region having the low breakdown voltage, and carriers of the breakdown current are collected through the carrier collecting region. The breakdown of the IGBT is further effectively prevented by forming a guard ring for suppressing electric field concentration around the region having the low breakdown voltage.
摘要翻译： 在半导体衬底上形成具有绝缘栅双极晶体管（IGBT）的半导体器件。 在基板的第一表面上形成基极区域和发射极，同时在基板的第二表面上形成集电极层。 在IGBT周围的第一表面上形成具有低击穿电压的区域，并且在具有低击穿电压的区域附近形成载流子收集区域。 由于在具有低击穿电压的区域中发生击穿，因此防止IGBT由于雪崩现象而分解，并且通过载流子收集区域收集击穿电流的载流子。 通过形成用于抑制具有低击穿电压的区域周围的电场浓度的保护环，进一步有效地防止了IGBT的击穿。
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