利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

37 条记录 (耗时 0.027 秒)

    Multilayer chip inductor and production method for same
    1.
    发明授权
    Multilayer chip inductor and production method for same 有权
    多层片式电感及其制作方法相同

    公开(公告)号：US08947189B2

    公开(公告)日：2015-02-03

    申请号：US13991690

    申请日：2011-10-19

    申请人： Yoshikazu Maruyama ,  Masataka Kohara ,  Kazuhiko Oyama

    发明人： Yoshikazu Maruyama ,  Masataka Kohara ,  Kazuhiko Oyama

    IPC分类号： H01F27/29 ,  H01F5/00 ,  H01F27/24 ,  H01F7/06 ,  H01F27/28 ,  H01F17/00 ,  H01F41/04

    CPC分类号： H01F27/2804 ,  H01F17/0013 ,  H01F41/041 ,  H01F41/043 ,  H01F2017/0073 ,  Y10T29/4902

    摘要： A group of magnetic sheets are stacked and connected via through-holes, on each of which magnetic sheets a circling pattern having connection parts at its corners and ends is formed to form a spiral coil pattern. Leader patterns each have a leader part formed at a position not overlapping with the circling parts of the coil pattern and connected to an external terminal electrode, as well as two connection parts that continue to the leader part and are formed at positions corresponding to the connection parts of the circling patterns, together with a cutout formed between the two connection parts. Magnetic sheets with the leader patterns are provided at the top and bottom of the laminate forming the coil pattern. The multilayer chip inductor can suppress decrease in core area caused by displacement due to the stacking.

    摘要翻译： 通过通孔堆叠并连接一组磁性片，每个磁性片形成在其角部和端部具有连接部分的环状图案以形成螺旋线圈图案。 引线图案各自具有形成在与线圈图案的环绕部分不重叠的位置并且连接到外部端子电极的引导部分，以及连续到引导部分并且形成在与连接相对应的位置处的两个连接部分 圆形图案的一部分，以及形成在两个连接部分之间的切口。 在形成线圈图案的层叠体的顶部和底部设置具有引导图案的磁性片。 多层芯片电感器可以抑制由堆叠引起的位移引起的芯部面积的减小。

    MULTILAYER CHIP INDUCTOR AND PRODUCTION METHOD FOR SAME
    2.
    发明申请
    MULTILAYER CHIP INDUCTOR AND PRODUCTION METHOD FOR SAME 有权
    多层芯片电感器及其生产方法

    公开(公告)号：US20140132385A1

    公开(公告)日：2014-05-15

    申请号：US13991690

    申请日：2011-10-19

    申请人： Yoshikazu Maruyama ,  Masataka Kohara ,  Kazuhiko Oyama

    发明人： Yoshikazu Maruyama ,  Masataka Kohara ,  Kazuhiko Oyama

    IPC分类号： H01F27/28 ,  H01F41/04

    CPC分类号： H01F27/2804 ,  H01F17/0013 ,  H01F41/041 ,  H01F41/043 ,  H01F2017/0073 ,  Y10T29/4902

    摘要： A group of magnetic sheets are stacked and connected via through-holes, on each of which magnetic sheets a circling pattern having connection parts at its corners and ends is formed to form a spiral coil pattern. Leader patterns each have a leader part formed at a position not overlapping with the circling parts of the coil pattern and connected to an external terminal electrode, as well as two connection parts that continue to the leader part and are formed at positions corresponding to the connection parts of the circling patterns, together with a cutout formed between the two connection parts. Magnetic sheets with the leader patterns are provided at the top and bottom of the laminate forming the coil pattern. The multilayer chip inductor can suppress decrease in core area caused by displacement due to the stacking

    摘要翻译： 通过通孔堆叠并连接一组磁性片，每个磁性片形成在其角部和端部具有连接部分的环状图案以形成螺旋线圈图案。 引线图案各自具有形成在与线圈图案的环绕部分不重叠的位置并且连接到外部端子电极的引导部分，以及连续到引导部分并且形成在与连接相对应的位置处的两个连接部分 圆形图案的一部分，以及形成在两个连接部分之间的切口。 在形成线圈图案的层叠体的顶部和底部设置具有引导图案的磁性片。 多层芯片电感器可以抑制由堆叠引起的位移引起的芯部面积的减小

    Nonvolatile memory device with reduced current consumption
    3.
    发明授权
    Nonvolatile memory device with reduced current consumption 有权
    具有降低电流消耗的非易失性存储器件

    公开(公告)号：US08259505B2

    公开(公告)日：2012-09-04

    申请号：US12789522

    申请日：2010-05-28

    申请人： Kazuhiko Oyama

    发明人： Kazuhiko Oyama

    IPC分类号： G11C16/04 ,  G11C7/02

    CPC分类号： G11C16/28

    摘要： A nonvolatile memory device includes one or more reference cell transistors, one or more memory cell transistors, and a current source circuit including three or more field effect transistors that have gates thereof connected together, the three or more field effect transistors including two or more field effect transistors and another field effect transistor, currents flowing through the two or more field effect transistors being combined to flow through the one or more reference cell transistors, and another field effect transistor having a drain thereof connected to one of the one or more memory cell transistors.

    摘要翻译： 非易失性存储器件包括一个或多个参考单元晶体管，一个或多个存储单元晶体管，以及包括三个或更多个其栅极连接在一起的场效应晶体管的电流源电路，所述三个或更多个场效应晶体管包括两个或更多个场 效应晶体管和另一个场效应晶体管，流经两个或更多个场效应晶体管的电流被组合以流过一个或多个参考单元晶体管，以及另一场效应晶体管，其漏极连接到一个或多个存储单元之一 晶体管。

    Communication apparatus and program provided with failure determining method and function
    6.
    发明申请
    Communication apparatus and program provided with failure determining method and function 有权

    公开(公告)号：US20060215525A1

    公开(公告)日：2006-09-28

    申请号：US11151196

    申请日：2005-06-14

    申请人： Kazuhiko Oyama ,  Koji Hanada

    发明人： Kazuhiko Oyama ,  Koji Hanada

    IPC分类号： G11B20/10

    CPC分类号： G06F11/0727 ,  G06F11/0757 ,  G06F11/079 ,  H04L69/28 ,  H04L69/40

    摘要： Disclosed is a method of determining a failure in an information system including a transmission apparatus for transmitting control information and a reception apparatus connected to the transmission apparatus in such a manner as to enable information to be transmitted and received for receiving the control information, the reception apparatus transmitting response information to the received control information, wherein the transmission apparatus obtains, as first clock time, clock time of the most recently transmitted control information if the response information to the control information cannot be obtained within predetermined time period, wherein the transmission apparatus obtains, as second clock time, later one of clock time of the response information most recently transmitted by the reception apparatus and clock time of the control information most recently received by the reception apparatus, and wherein the transmission apparatus determines failure location based on the first clock time and the second clock time.