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公开(公告)号：US06803810B2
公开(公告)日：2004-10-12
申请号：US10300592
申请日：2002-11-21
IPC分类号： G05F110
CPC分类号： H04B1/40 , H04W52/028 , Y02D70/24 , Y02D70/40
摘要： A proposed semiconductor device is directed to making unnecessary circuit operation inactive to reduce power consumption because of leakage current. The device is functionally divided into blocks. The power supply systems of the blocks are divided into a non-controlled power supply group in which power is always on and controlled power supply groups in each of which groups a supply of power can be turned on/off independently. When a power supply system control part of the non-controlled power supply group outputs a control signal for power on, a power switch part turns on to release the controlled power supply group from the sleep mode, so that the first processing part starts intermittent operation. Only when it is determined that a first next-processing necessity determining part determines necessity of the next processing, a control signal is generated to activate the next power supply group. The blocks unnecessary for processing are not supplied with power, so that no leakage current flows and power consumption because thereof can be reduced.
摘要翻译： 所提出的半导体器件旨在使不必要的电路操作无效以便由于泄漏电流而降低功耗。 该设备在功能上划分为块。 块的电源系统分为电源始终接通的非受控电源组，每个组中的电源组可独立接通/断开。 当非受控电源组的电源系统控制部分输出用于接通电源的控制信号时，电源开关部分接通以将受控电源组从睡眠模式释放，使得第一处理部分开始间歇操作 。 只有当确定第一下一个处理必要性确定部分确定下一个处理的必要性时，才产生控制信号以激活下一个电源组。 不需要处理的块被供电，所以不会有泄漏电流流动，因此可以减少功耗。
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公开(公告)号：US06883092B2
公开(公告)日：2005-04-19
申请号：US10157992
申请日：2002-05-31
CPC分类号： G06F9/4401
摘要： A processor and method of booting the processor in which dispensable circuit operation is eliminated to reduce power consumption. A first expected check-sum value relating to instructions and table data and a second expected check-sum value relating only to instructions are held in a boot ROM. When power is turned on, if a power-on determination circuit determines that the power has been turned on for a system, a read selection circuit loads instructions and the table data into an instruction storage memory and a table data storage memory and a check-sum performing circuit performs check-sum using the first expected check-sum value. In the case where the power has been turned on for periodic operation, instructions are loaded into the instruction storage memory, check-sum is performed using the second expected check-sum value, and table data that was saved in a backup memory is loaded into the table data storage memory. Thus, the time required for loading from the boot ROM for the periodic operation decreases.
摘要翻译： 引导处理器的处理器和方法，其中消除了可分配的电路操作以降低功耗。 与指令和表数据相关的第一预期校验和值和仅与指令相关的第二预期校验和值被保存在引导ROM中。 当电源接通时，如果上电确定电路确定系统的电源已经接通，则读选择电路将指令和表数据加载到指令存储存储器和表数据存储存储器中， 总和执行电路使用第一预期校验和值来执行校验和。 在电源已经接通周期性操作的情况下，指令被加载到指令存储器中，使用第二预期校验和值进行校验和，并将保存在备用存储器中的表数据加载到 表数据存储内存。 因此，用于周期性操作的从引导ROM加载所需的时间减少。
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公开(公告)号：US06980585B2
公开(公告)日：2005-12-27
申请号：US10102814
申请日：2002-03-22
IPC分类号： H04B1/707 , H04B1/7085 , H04B1/7093 , H04B1/7117 , H04L1/69
CPC分类号： H04B1/7113 , H04B2201/7071
摘要： A receiving unit, receiving method, and semiconductor device that reduce the size of circuits in a receiving unit. A receiving section receives signals sent from a base station and transmitted through a plurality of paths. A path tracking section detects timing of each of the plurality of paths through which the signals received by the receiving section were transmitted. A demodulating section demodulates the received signals by performing a despreading process according to the timing of the plurality of paths detected by the path tracking section. A correlation value calculating section calculates a correlation value between the received signals and a spreading code. A destination selecting section provides output from the correlation value calculating section to the path tracking section in the case of performing a path tracking process by the path tracking section and provides output from the correlation value calculating section to the demodulating section in the case of demodulating the received signals by the demodulating section.
摘要翻译： 一种减小接收单元中的电路尺寸的接收单元，接收方法和半导体器件。 接收部分接收从基站发送并通过多个路径发送的信号。 路径跟踪部分检测发送由接收部分接收的信号的多个路径中的每一个的定时。 解调部通过根据由路径追踪部检测出的多个路径的定时进行解扩处理来解调接收信号。 相关值计算部分计算接收信号和扩展码之间的相关值。 目的地选择部分在路径跟踪部分执行路径跟踪处理的情况下，将相关值计算部分的输出提供给路径跟踪部分，并且在解调该解调部分的情况下将相关值计算部分的输出提供给解调部分 由解调部分接收信号。
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4.发明授权Semiconductor integrated circuit with function to start and stop supply of clock signal 有权具有启动和停止时钟信号供电功能的半导体集成电路公开(公告)号：US06639436B2
公开(公告)日：2003-10-28
申请号：US10097619
申请日：2002-03-15
IPC分类号： H03L700
CPC分类号： G06F1/3237 , G06F1/3203 , Y02D10/128
摘要： A semiconductor integrated circuit includes a plurality of functional blocks, each of which starts and stops an operation thereof in response to assertion and negation, respectively, of a corresponding command signal, a clock generation circuit which generates a clock signal, a clock control circuit which starts supplying the clock signal to each of the functional blocks in response to the assertion of the corresponding command signal, and stops supplying the clock signal to each of the functional blocks in response to the negation of the corresponding command signal.
摘要翻译： 半导体集成电路包括多个功能块，每个功能块分别响应于对应的命令信号的断言和否定而启动和停止其操作，产生时钟信号的时钟产生电路，时钟控制电路 响应于相应的命令信号的断言，开始向每个功能块提供时钟信号，并且响应于对应的命令信号的否定而停止向每个功能块提供时钟信号。
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5.发明授权公开(公告)号：US06973004B2
公开(公告)日：2005-12-06
申请号：US10346103
申请日：2003-01-17
申请人： Jun Iwata , Shoji Taniguchi , Koichi Kuroiwa , Yoshikazu Yamada
发明人： Jun Iwata , Shoji Taniguchi , Koichi Kuroiwa , Yoshikazu Yamada
CPC分类号： G06F1/3203 , G06F1/3287 , H04W52/028 , Y02D10/171 , Y02D70/24
摘要： A semiconductor device that quickly saves data stored in an area to which power is supplied intermittently. Power is supplied intermittently to a first area. Power is supplied continuously to a second area. A memory is located in the second area. A save circuit saves data used in the first area in the memory before the supply of power being stopped. A restoration circuit restores data which has been saved in the memory to a predetermined circuit in the first area. A power supply control circuit supplies power to the memory if data has been saved in the memory. Otherwise the power supply control circuit stops the supply of power to the memory.
摘要翻译： 一种半导体器件，其能够快速地保存间歇地供电的区域中存储的数据。 间歇地供电到第一区域。 电源连续供应到第二个区域。 内存位于第二区。 节电电路在电源供电停止之前，将存储器中第一个区域中使用的数据保存在存储器中。 恢复电路将保存在存储器中的数据恢复到第一区域中的预定电路。 如果数据已被保存在存储器中，则电源控制电路向存储器供电。 否则电源控制电路停止向存储器供电。
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公开(公告)号：US07035318B2
公开(公告)日：2006-04-25
申请号：US10105191
申请日：2002-03-26
CPC分类号： H04B1/7115 , H04B1/712
摘要： A receiving unit for receiving a CDMA system signal having a plurality of multipath components is intended to reduce the size. A receiving section receives a CDMA system signal. A storage section stores the signal received by the receiving section. A demodulation section demodulates each of multipath components included in the received signal stored in the storage section with a despreading code. A control section controls for demodulating a plurality of the multipath components by causing the demodulation section to perform a time division multiplex process. A Rake combining section performs the maximal ratio combining of output from the demodulation section to generate a demodulated signal.
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公开(公告)号：US06947961B2
公开(公告)日：2005-09-20
申请号：US10078368
申请日：2002-02-21
CPC分类号： G06F9/3001
摘要： There are provided an arithmetic unit and a receiver unit which execute an arithmetic operation at a high speed and allow reduction of the size thereof. An input section inputs data of the data group. First to n-th (n>1) storage sections have a capacity capable of storing at least part or all of the data group. A readout section selects one of the first to n-th storage sections and reads out therefrom a data group already stored therein. An arithmetic section performs a predetermined arithmetic operation between the data group read out by the readout section and the data group newly inputted by the input section. A writing section writes a result of the predetermined arithmetic operation by the arithmetic section in a predetermined one of the storage sections, which is not selected by the reading section as the one from which the data group already stored therein is to be read out.
摘要翻译： 提供了一种算术单元和接收器单元，其高速执行算术运算并允许其尺寸的减小。 输入部分输入数据组的数据。 第一至第n（n> 1）个存储部具有能够存储至少部分或全部数据组的容量。 读出部选择第一至第n存储部中的一个，并从其中读出已经存储在其中的数据组。 算术部分在由读出部分读出的数据组与由输入部分新输入的数据组之间执行预定的算术运算。 写入部分将未被读取部分选择的预定的一个存储部分中的运算部分的预定算术运算的结果写入其中已经存储在其中的数据组被读出。
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公开(公告)号：US07032161B2
公开(公告)日：2006-04-18
申请号：US10223216
申请日：2002-08-20
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/09 , H03M13/23 , H03M13/39 , H03M13/41
摘要： An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.
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公开(公告)号：US06493844B1
公开(公告)日：2002-12-10
申请号：US09311722
申请日：1999-05-14
IPC分类号： H03M1300
CPC分类号： H03M13/091 , H03M13/09 , H03M13/23 , H03M13/39 , H03M13/41
摘要： An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string generated at the transmitter so that errors in the reception bit string are detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.
摘要翻译： 接收机的误差检测器包括反馈移位寄存器。 反馈移位寄存器中的移位方向与通过使用指定的生成多项式生成传输位串时的发送器处的移位方向相反。 接收比特串以相反的顺序被输入到反馈移位寄存器，以便在发送器处产生的发送比特串，从而通过获得余数来检测接收比特串中的错误。 接收机处的另一个误差检测器包括第一和第二反馈移位寄存器。 第一和第二反馈移位寄存器中的相应移位方向与发送器在生成传输位串时的移位方向相同且相反。 接收比特串以与生成发送比特串相同的顺序输入到第一反馈移位寄存器，而接收比特串以相反的顺序被输入到第二反馈移位寄存器，以产生发送比特串 。 通过比较由第一和第二反馈移位寄存器获得的各个余数来检测接收位串中的错误。 这减少了错误检测所需的处理时间，并提高了检测传输数据中错误的效率。
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10.发明授权State machine in which subsequent state can be directly inputted externally and transition can be stopped retaining the current state 失效可以直接在外部输入后续状态的状态机，可以停止保持当前状态的转换
公开(公告)号：US5778251A
公开(公告)日：1998-07-07
申请号：US975071
申请日：1997-11-20
申请人： Koichi Kuroiwa , Shoji Taniguchi
发明人： Koichi Kuroiwa , Shoji Taniguchi
IPC分类号： G06F13/00 , G06F11/26 , G06F11/267 , H04L29/02 , G06F11/00
CPC分类号： G06F11/2236 , G06F11/26
摘要： A state machine that can be tested easily is disclosed. A state machine has a latch for storing data representing an intended state and a state control unit for producing data representing a subsequent state according to an intended state provided by the latch and a detection signal, and makes state transitions consecutively. The state machine comprises a state data input unit for inputting data representing an intended state directly from an external unit, a selector for selecting either data provided by the state control unit or data provided by the state data input unit so as to supply selected data as data representing a subsequent state to the latch, and a control data input unit for externally inputting control data for use in controlling the selection performed by the selector. After data representing an intended state is fed to the state data input unit, when control data requesting the selector to select data provided by the state data input unit and to send the data to the latch is input via the control data input unit, the latch latches data representing an intended state synchronously with a clock and thus retains the intended state.
摘要翻译： 公开了可以容易地测试的状态机。 状态机具有用于存储表示预期状态的数据的锁存器和用于根据锁存器提供的预期状态产生表示后续状态的数据的状态控制单元和检测信号，并且连续地进行状态转换。 状态机包括用于直接从外部单元输入表示预期状态的数据的状态数据输入单元，选择器，用于选择由状态控制单元提供的数据或由状态数据输入单元提供的数据，以便将选择的数据提供为 表示对锁存器的后续状态的数据;以及控制数据输入单元，用于从外部输入用于控制由选择器执行的选择的控制数据。 在表示预期状态的数据被馈送到状态数据输入单元之后，当经由控制数据输入单元输入请求选择器选择器选择由状态数据输入单元提供并将数据发送到锁存器的控制数据时， 与时钟同步地锁定表示预期状态的数据，从而保持预期状态。
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