公开(公告)号：US20130062680A1

公开(公告)日：2013-03-14

申请号：US13413952

申请日：2012-03-07

申请人： Yoshiko KATO ,  Masato Endo ,  Mitsuhiko Noda ,  Mitsuhiro Noguchi

发明人： Yoshiko KATO ,  Masato Endo ,  Mitsuhiko Noda ,  Mitsuhiro Noguchi

IPC分类号： H01L27/105 ,  H01L21/8239

CPC分类号： H01L21/76229 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.

摘要翻译： 根据一个实施例，半导体存储器包括设置在半导体衬底中的存储单元阵列中的存储单元，其包括由第一隔离绝缘体围绕的第一有源区，设置在半导体中的晶体管区中的晶体管 并且其包括由第二隔离绝缘体围绕的第二有源区。 第二隔离绝缘体包括第一膜和在第一膜和第二有源区之间的第二膜，并且第一膜的上表面比第二膜的上表面更靠近半导体衬底的底部。

公开(公告)号：US20100301426A1

公开(公告)日：2010-12-02

申请号：US12788784

申请日：2010-05-27

申请人： Hiroyuki KUTSUKAKE ,  Kenji GOMIKAWA ,  Yoshiko KATO ,  Mitsuhiro NOGUCHI ,  Masato ENDO

发明人： Hiroyuki KUTSUKAKE ,  Kenji GOMIKAWA ,  Yoshiko KATO ,  Mitsuhiro NOGUCHI ,  Masato ENDO

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/41775 ,  H01L29/7838

摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

摘要翻译： 半导体存储器件包括第一晶体管。 第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。 沟道区具有第一杂质浓度。 源区和漏区具有第二杂质浓度。 重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。 接触区域具有第四杂质浓度。 杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。 杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

公开(公告)号：US20070187797A1

公开(公告)日：2007-08-16

申请号：US11671229

申请日：2007-02-05

申请人： Yoshiko KATO ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi

发明人： Yoshiko KATO ,  Shigeru Ishibashi ,  Mitsuhiro Noguchi

IPC分类号： H01L29/00

CPC分类号： H01L21/823807 ,  H01L21/823857 ,  H01L21/823892

摘要： A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks.

摘要翻译： 根据本发明的实施例的半导体器件包括第一导电类型的第一半导体区域，形成在第一半导体区域中的第二导电类型的第一MIS晶体管，第二导电类型的第二半导体区域，以及 形成在第二半导体区域中的第一导电类型的第二MIS晶体管。 第一MIS晶体管的第一栅极绝缘层比第二MIS晶体管的第二栅极绝缘层厚，并且第二MIS晶体管的沟道区中的第一导电类型的杂质的轮廓具有峰值。

公开(公告)号：US20090010036A1

公开(公告)日：2009-01-08

申请号：US12164486

申请日：2008-06-30

申请人： Yoshiko KATO ,  Mitsuhiro Noguchi

发明人： Yoshiko KATO ,  Mitsuhiro Noguchi

IPC分类号： G11C5/02

CPC分类号： G11C5/025 ,  G11C16/0483

摘要： A semiconductor memory includes a memory cell array area having a memory cell, a word line contact area adjacent to the memory cell array area, a word line arranged straddling the memory cell array area and the word line contact area, a contact hole provided on the word line in the word line contact area, and a word line driver connected to the word line via the contact hole. A size of the contact hole is larger than a width of the word line, and the lowest parts of the contact hole exist on a position lower than a top surface of the word line and higher than a bottom surface of the word line.

摘要翻译： 半导体存储器包括具有存储单元的存储单元阵列区域，与存储单元阵列区域相邻的字线接触区域，跨过存储单元阵列区域排列的字线和字线接触区域， 字线接触区域中的字线，以及经由接触孔连接到字线的字线驱动器。 接触孔的尺寸大于字线的宽度，并且接触孔的最低部分存在于比字线的顶表面低的位置，并且高于字线的底表面。

公开(公告)号：US20080073672A1

公开(公告)日：2008-03-27

申请号：US11858634

申请日：2007-09-20

申请人： Yoshiko KATO ,  Mitsuhiro Noguchi

发明人： Yoshiko KATO ,  Mitsuhiro Noguchi

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11526

摘要： A nonvolatile semiconductor memory concerning an example of the present invention comprises a cell array, a plurality of conducting wires extending from the cell array to a lead area, and a plurality of contact holes to arranged in the lead area so that a distance from the end of the cell array sequentially increases from one to the other of the plurality of conducting wires, each of the plurality of conducting wires having a first conducting wire portion having a first conducting wire width, a second conducting wire portion connected to the contact hole and having a second conducting wire width smaller than the first conducting wire width, and a third conducting wire portion electrically connecting the first conducting wire portion to the second conducting wire portion.

摘要翻译： 关于本发明的实例的非易失性半导体存储器包括单元阵列，从单元阵列延伸到引导区域的多个导线以及布置在引导区域中的多个接触孔，使得距离端部的距离 所述多个导线中的每个导线具有具有第一导线宽度的第一导线部分，连接到所述接触孔的第二导线部分，并且具有 第二导线宽度小于第一导线宽度;以及第三导线部分，其将第一导线部分电连接到第二导线部分。

公开(公告)号：US20120178229A1

公开(公告)日：2012-07-12

申请号：US13426664

申请日：2012-03-22

申请人： Yoshiko KATO ,  Mitsuhiro Noguchi

发明人： Yoshiko KATO ,  Mitsuhiro Noguchi

IPC分类号： H01L21/8239

CPC分类号： H01L21/26586 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.

摘要翻译： 半导体存储器件包括第一有源区，第二有源区，第一元件隔离区和第二元件隔离区。 第一有源区形成在半导体衬底中。 第二有源区形成在半导体衬底中。 第一元件隔离区域使彼此相邻的第一有源区域电隔离。 第二元件隔离区域将彼此相邻的第二有源区域电隔离。 与第二元件隔离区域的侧面接触的第二有源区域的一部分中的杂质浓度高于第二有源区域的中心部分的杂质浓度，第一有源区域的一部分中的杂质浓度在 与第一元件隔离区域的侧面的接触与第一有源区域中的相同。

公开(公告)号：US20110062509A1

公开(公告)日：2011-03-17

申请号：US12725848

申请日：2010-03-17

申请人： Yoshiko KATO ,  Mitsuhiro Noguchi ,  Hiroyuki Kutsukake

发明人： Yoshiko KATO ,  Mitsuhiro Noguchi ,  Hiroyuki Kutsukake

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L27/11529 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L29/1083 ,  H01L29/66825

摘要： A semiconductor memory device includes: a semiconductor substrate; a plurality of element isolation insulators disposed in parts of an upper layer portion of the semiconductor substrate and dividing the upper layer portion into a plurality of active areas extended in one direction; tunnel insulating films provided on the active areas: charge storage members provided on the tunnel insulating films; and control gate electrodes provided on the charge storage members. A width of a middle portion of one of the active areas in the up-to-down direction being smaller than a width of a portion of the active areas upper of the middle portion and a width of a portion of the active areas below the middle portion.

摘要翻译： 半导体存储器件包括：半导体衬底; 多个元件隔离绝缘体，设置在所述半导体衬底的上层部分的一部分中，并将所述上层部分分成沿一个方向延伸的多个有效区域; 设置在有源区域上的隧道绝缘膜：设置在隧道绝缘膜上的电荷存储构件; 以及设置在电荷存储部件上的控制栅电极。 一个有源区域的上下方向的中间部分的宽度小于中间部分的有效区域的一部分的宽度，以及在中间部分之下的有效区域的一部分的宽度 一部分。

公开(公告)号：US20100013028A1

公开(公告)日：2010-01-21

申请号：US12501726

申请日：2009-07-13

申请人： Yoshiko KATO ,  Hiroyuki KUTSUKAKE

发明人： Yoshiko KATO ,  Hiroyuki KUTSUKAKE

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/823481 ,  H01L21/823462 ,  H01L27/088

摘要： A semiconductor device with a high-voltage transistor and a low-voltage transistor includes an isolation insulating film between a first element region of the high-voltage transistor and a second element region of the low-voltage transistor, a first gate insulating film on a semiconductor substrate in the first element region, a first gate electrode on the first gate insulating film, a second gate insulating film on the semiconductor substrate in the second element region, and a second gate electrode on the second gate insulating film. The isolation insulating film includes a first isolation region adjacent to a surrounding area of the first element region and a second isolation region adjacent to a surrounding area of the second element region. A bottom of the second isolation region is lower than a bottom of the first isolation region. The first gate insulating film is thicker than the second gate insulating film.

摘要翻译： 具有高压晶体管和低压晶体管的半导体器件包括在高压晶体管的第一元件区域和低压晶体管的第二元件区域之间的隔离绝缘膜，第一栅极绝缘膜 第一元件区域中的半导体衬底，第一栅极绝缘膜上的第一栅极电极，第二元件区域中的半导体衬底上的第二栅极绝缘膜，以及第二栅极绝缘膜上的第二栅极电极。 隔离绝缘膜包括与第一元件区域的周围区域相邻的第一隔离区域和与第二元件区域的周围区域相邻的第二隔离区域。 第二隔离区域的底部低于第一隔离区域的底部。 第一栅极绝缘膜比第二栅极绝缘膜厚。

公开(公告)号：US20100314677A1

公开(公告)日：2010-12-16

申请号：US12724802

申请日：2010-03-16

申请人： Yoshiko KATO ,  Hiroyuki Kutsukake ,  Kikuko Sugimae ,  Yasuhiko Matsunaga

发明人： Yoshiko KATO ,  Hiroyuki Kutsukake ,  Kikuko Sugimae ,  Yasuhiko Matsunaga

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11521

摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first device isolation/insulation film formed in a trench, the trench formed in the semiconductor layer, with a first direction taken as a longitudinal direction; a device formation region formed by separating the semiconductor layer by the first device isolation/insulation film with the first direction taken as a longitudinal direction; and a memory transistor disposed on the device formation region. The first device isolation/insulation film and the device formation region have an impurity of a first conductivity type. An impurity concentration of the impurity of the first conductivity type in the first device isolation/insulation film is higher than that in the device formation region.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 形成在半导体衬底上的半导体层; 形成在沟槽中的第一器件隔离/绝缘膜，形成在半导体层中的沟槽，第一方向作为纵向方向; 通过第一装置隔离/绝缘膜将第一方向作为纵向方向分离半导体层而形成的器件形成区域; 以及设置在器件形成区域上的存储晶体管。 第一器件隔离/绝缘膜和器件形成区具有第一导电类型的杂质。 第一器件隔离/绝缘膜中的第一导电类型的杂质的杂质浓度高于器件形成区域中的杂质浓度。

公开(公告)号：US20100270606A1

公开(公告)日：2010-10-28

申请号：US12765477

申请日：2010-04-22

申请人： Hiroyuki KUTSUKAKE ,  Takayuki TOBA ,  Yoshiko KATO ,  Kenji GOMIKAWA ,  Haruhiko KOYAMA

发明人： Hiroyuki KUTSUKAKE ,  Takayuki TOBA ,  Yoshiko KATO ,  Kenji GOMIKAWA ,  Haruhiko KOYAMA

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

摘要翻译： 在存储单元阵列区域周围形成外围电路区域。 外围电路区域具有元件区域，隔离元件区域的元件隔离区域和形成在每个元件区域中并包括在沟道宽度方向上延伸的栅电极的场效应晶体管。 栅电极的端部和角部位于元件隔离区上。 栅电极的角部的曲率半径比从沟道宽度方向的元件区域的端部到沟道宽度方向的栅电极的端部的长度小，并且小于85nm 。