-
公开(公告)号：US20050038911A1
公开(公告)日：2005-02-17
申请号：US10945934
申请日：2004-09-22
CPC分类号： H04L67/2814 , G06Q10/10 , H04L67/2823 , H04L67/327
摘要： A cooperative system includes a plurality of information systems and a hub system connected to the plurality of systems. The hub system receives a message from a first information system, determines necessity of message conversion and a kind of conversion, converts the message to a form suitable for a second information system which is destination, only when message conversion is necessary, and transmits the message to a second information system. The hub system may determine whether flow control determining a flow and destination of a message received from the first information system based on a class of the message should be conducted, and conduct flow control only when it has been determined that flow control should be conducted.
摘要翻译： 协作系统包括多个信息系统和连接到多个系统的集线器系统。 集线器系统从第一信息系统接收消息，确定消息转换的必要性和一种转换，只有当需要消息转换时，将消息转换成适合作为目的地的第二信息系统的形式，并且传送消息 到第二个信息系统。 集线器系统可以确定是否应该进行基于消息类别来确定从第一信息系统接收的消息的流量和目的地的流量控制，并且仅在已经确定应当进行流量控制时才进行流量控制。
-
公开(公告)号：US06578159B1
公开(公告)日：2003-06-10
申请号：US09443102
申请日：1999-11-18
申请人： Makoto Kitagawa , Tetsuya Hashimoto , Akira Kito
发明人： Makoto Kitagawa , Tetsuya Hashimoto , Akira Kito
IPC分类号： G06F1100
CPC分类号： G06F11/1474 , Y10S707/99953
摘要： In a transaction processing method for executing a series of a plurality of transactions in accordance with a workflow, compensation processing is registered as an error recovery flow when each transaction is executed, the compensation processing executing error recovery processing when an error occurs while the transaction is executed, and a series of compensation processing is executed in parallel in accordance with the registered error recovery flow when an error occurs while any of the transaction is executed.
摘要翻译： 在用于根据工作流执行一系列事务的事务处理方法中，当执行每个事务时，将补偿处理记录为错误恢复流程，当事务发生时发生错误时，补偿处理执行错误恢复处理 并且当执行任何交易时发生错误时，根据注册错误恢复流程并行执行一系列补偿处理。
-
公开(公告)号：US08379430B2
公开(公告)日：2013-02-19
申请号：US12923978
申请日：2010-10-19
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/0061 , G11C2013/0054 , G11C2213/11 , G11C2213/56 , G11C2213/79
摘要： A memory device includes: a memory unit in which an electric charge discharging rate between two electrodes is different in accordance with logic of stored information; a sense amplifier that detects the logic of the information by comparing a discharge electric potential of a wiring to which one electrode of the memory unit is connected with a reference electric potential; and a replica circuit that has a replica unit emulating the memory unit and controls a sense timing of the sense amplifier in accordance with a discharge rate of the replica unit.
摘要翻译： 存储装置包括：存储单元，其中两个电极之间的电荷放电速率根据所存储信息的逻辑而不同; 读出放大器，通过将存储单元的一个电极与其连接的布线的放电电位与参考电位进行比较来检测信息的逻辑; 以及复制电路，其具有仿真存储器单元的复制单元，并且根据复制单元的放电速率来控制读出放大器的感测时序。
-
公开(公告)号：US20120218809A1
公开(公告)日：2012-08-30
申请号：US13397282
申请日：2012-02-15
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2213/79
摘要： A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from the storage elements by changing the resistance state thereof, the read operation involving reading the information from the storage elements; wherein the drive portion includes an amplifier configured to output a read signal upon execution of the read operation, a constant current load, and a control portion configured to perform the resistance change operation and a direct verify operation on the storage elements, the direct verify operation involving carrying out, subsequent to the resistance change operation, the read operation for verifying whether the writing or erasing of the information to or from the storage elements has been normally accomplished.
摘要翻译： 存储装置包括：多个存储元件，其被配置为根据施加的电压使其电阻状态发生变化; 以及驱动部，被配置为执行电阻变化操作和读取操作，所述电阻改变操作涉及通过改变其电阻状态来从存储元件写入或擦除信息，所述读取操作涉及从存储元件读取信息; 其特征在于，所述驱动部具有：放大器，被配置为在执行所述读取操作时输出读取信号;恒定电流负载;以及被配置为对所述存储元件执行电阻变化操作和直接验证操作的控制部，所述直接验证操作 涉及在电阻变化操作之后进行用于验证是否正常地完成对存储元件的写入或擦除信息的读取操作。
-
5.发明授权Nonvolatile semiconductor memory device and method for performing verify write operation on the same 有权非易失性半导体存储器件及其执行验证写入操作的方法公开(公告)号：US08102716B2
公开(公告)日：2012-01-24
申请号：US12654783
申请日：2010-01-04
IPC分类号： G11C11/34
CPC分类号： G11C13/0011 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined number of memory cells constituting a write cell unit, writing data collectively to the predetermined number of memory cells, and verifying the written data, the driver circuit further performing the verify write operation repeatedly until all memory cells within the write cell unit are found to have passed the verification.
摘要翻译： 这里公开了一种包括多个存储单元的非易失性半导体存储器件; 以及驱动电路，被配置为在循环中执行验证写入操作，包括从多个存储器单元的阵列中选择构成写入单元单元的预定数量的存储单元，将数据共同地写入预定数量的存储单元，以及验证 写入的数据，驱动器电路进一步执行验证写入操作，直到发现写入单元单元内的所有存储单元已经通过验证。
-
公开(公告)号：US20110305068A1
公开(公告)日：2011-12-15
申请号：US13116590
申请日：2011-05-26
IPC分类号： G11C11/00
CPC分类号： H01L45/085 , G11C13/0026 , G11C13/0069 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2472 , H01L45/1233 , H01L45/1266 , H01L45/145
摘要： A resistance random access change memory device includes: a memory cell array in which plural memory cells having current paths with series-connected access transistors and variable resistive elements are two-dimensionally arranged; plural bit lines that connect one ends of the current paths; plural source lines that connect the other ends of the current paths; and plural word lines that control conduction and non-conduction of the access transistors, wherein bit line contacts are shared between two memory cells to which the word lines are adjacently provided, and pairs of memory cells are formed, all of the pairs of memory cells connected to the adjacent two bit lines are connected to the corresponding source lines via individual source line contacts, and the source lines are formed by a wiring layer upper than that of the bit lines with a larger pitch than that of the bit lines.
摘要翻译： 电阻随机存取改变存储器件包括：存储单元阵列，其中具有串联连接的存取晶体管和可变电阻元件的电流路径的多个存储单元被二维布置; 连接当前路径的一端的多个位线; 连接当前路径的另一端的多条源极线; 以及控制存取晶体管的导通和非导通的多个字线，其中位线接触在相邻设置有字线的两个存储单元之间共享，并且形成存储单元对，所有存储单元对 连接到相邻的两条位线通过各个源极线接触连接到相应的源极线，并且源极线由比位线的间距高于位线的布线层形成。
-
公开(公告)号：US20110026332A1
公开(公告)日：2011-02-03
申请号：US12805089
申请日：2010-07-12
申请人： Makoto Kitagawa
发明人： Makoto Kitagawa
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C7/08 , G11C13/0011 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2211/5642 , G11C2213/79
摘要： Disclosed herein is a semiconductor memory device including: a bit line and a sense line; a data storage element having a data storage state changing in accordance with a voltage applied to the bit line; a first switch for controlling connection of the sense line to the bit line; a data latch circuit having a second data holding node and a first data holding node connected to the sense line; and a second switch for controlling connection of the second data holding node of the data latch circuit to the bit line.
摘要翻译： 本文公开了一种半导体存储器件，包括：位线和感测线; 数据存储元件，其具有根据施加到所述位线的电压而改变的数据存储状态; 用于控制感测线与位线的连接的第一开关; 数据锁存电路，具有第二数据保持节点和连接到感测线的第一数据保持节点; 以及用于控制数据锁存电路的第二数据保持节点与位线的连接的第二开关。
-
8.发明申请Nonvolatile semiconductor memory device and method for performing verify write operation on the same 有权非易失性半导体存储器件及其执行验证写入操作的方法公开(公告)号：US20100195370A1
公开(公告)日：2010-08-05
申请号：US12654783
申请日：2010-01-04
CPC分类号： G11C13/0011 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： Disclosed herein is a nonvolatile semiconductor memory device including a plurality of memory cells; and a driver circuit configured to perform a verify write operation in a cycle including selecting from an array of the plurality of memory cells a predetermined number of memory cells constituting a write cell unit, writing data collectively to the predetermined number of memory cells, and verifying the written data, the driver circuit further performing the verify write operation repeatedly until all memory cells within the write cell unit are found to have passed the verification.
摘要翻译： 这里公开了一种包括多个存储单元的非易失性半导体存储器件; 以及驱动电路，被配置为在循环中执行验证写入操作，包括从多个存储器单元的阵列中选择构成写入单元单元的预定数量的存储单元，将数据共同地写入预定数量的存储单元，以及验证 写入的数据，驱动器电路进一步执行验证写入操作，直到发现写入单元单元内的所有存储单元已经通过验证。
-
公开(公告)号：US07756978B2
公开(公告)日：2010-07-13
申请号：US11129332
申请日：2005-05-16
IPC分类号： G06F15/177 , G06F15/173 , G06F11/00
CPC分类号： H04L67/1008 , H04L67/1002 , H04L67/1012 , H04L67/1029 , H04L67/125
摘要： A multiplicity adjustment agent collects request information database from a sub-system including an element of a system to be monitored. An individual sub-system's multiplicity adjustment server sorts and merges request information collected from each sub-system for each element/request path. An integrated multiplicity analysis server calculates a necessary multiplicity on the basis of the request information.
摘要翻译： 多重调整代理从包括要监视的系统的元素的子系统收集请求信息数据库。 单个子系统的多重调整服务器对每个子系统针对每个元素/请求路径收集的请求信息进行排序和合并。 综合多重分析服务器根据请求信息计算必要的多重性。
-
10.发明申请SYSTEM INFRASTRUCTURE STRUCTURE FORMULATION SUPPORTING SYSTEM AND SUPPORTING METHOD 审中-公开系统基础结构配置支持系统和支持方法公开(公告)号：US20080148220A1
公开(公告)日：2008-06-19
申请号：US11754453
申请日：2007-05-29
IPC分类号： G06F9/44
摘要： A system infrastructure structure formulation supporting method in which based on quality requirements, formulated examples of system infrastructure structures up to the present are grouped into a database for storing the system infrastructure structures, then being stored into a group management area in advance. At the time of a new formulation, demands presented with an expression which user uses are accepted from an input/output terminal. Then, the demands are converted into quality requirements of the system by making reference to a demand-contents management table, a quality-requirement management table, and a demand-quality-requirement correspondence table stored in a reference information storage area. Next, using the quality requirements acquired, a group stored in the group management area is selected. Moreover, elements within the group are selected from a grouping table, then sequentially presenting the formulated examples having high degrees of similarity.
摘要翻译： 一种基于质量要求的系统基础结构配置支持方法，将目前的系统基础设施结构的制定示例分组为用于存储系统基础设施结构的数据库，然后预先存储到组管理区域中。 在新制定时，从输入/输出终端接受用户使用的表达式的请求。 然后，通过参照存储在参考信息存储区域中的需求内容管理表，质量要求管理表和需求质量要求对应表，将需求转换为系统的质量要求。 接下来，使用获取的质量要求，选择存储在组管理区域中的组。 此外，组内的元素从分组表中选择，然后顺序呈现具有高度相似度的配制实施例。
-
-
-
-
-
-
-
-
-
搜索结果
91 条记录 (耗时 0.029 秒)