公开(公告)号：US06690000B1

公开(公告)日：2004-02-10

申请号：US09452596

申请日：1999-12-01

申请人： Yoshinori Muramatsu ,  Susumu Kurosawa ,  Yasutaka Nakashiba ,  Tsuyoshi Nagata

发明人： Yoshinori Muramatsu ,  Susumu Kurosawa ,  Yasutaka Nakashiba ,  Tsuyoshi Nagata

IPC分类号： H01L2700

CPC分类号： H04N5/3594 ,  H04N5/374

摘要： According to an image sensor disclosed, a pixel circuit includes a photo-diode 14 for generating a photo-electric conversion voltage which corresponds to an input optical level, a transistor 11 which is activated in response to a Reset signal RST, to initialize the photo-diode 14 from a power supply VDD, a transistor 12 which, when connected between the power supply VDD and a bit line BL, amplifies a photo-electric conversion voltage and outputs it onto the bit line BL, and a transistor 13 which is activated by a word-line readout control signal WL, to interconnect the transistor 12 and the bit line BL, in which the transistor 11 is of a depletion type.

摘要翻译： 根据所公开的图像传感器，像素电路包括用于产生对应于输入光学电平的光电转换电压的光电二极管14，响应于复位信号RST激活的晶体管11来初始化照片 来自电源VDD的晶体管12，当连接在电源VDD和位线BL之间时，放大光电转换电压并将其输出到位线BL上的晶体管12和被激活的晶体管13 通过字线读出控制信号WL将晶体管12与晶体管11为耗尽型的位线BL互连。

公开(公告)号：US06576882B2

公开(公告)日：2003-06-10

申请号：US10173874

申请日：2002-06-19

申请人： Yoshinori Muramatsu ,  Susumu Kurosawa ,  Hiroaki Ohkubo ,  Tsuyoshi Nagata ,  Yasutaka Nakashiba

发明人： Yoshinori Muramatsu ,  Susumu Kurosawa ,  Hiroaki Ohkubo ,  Tsuyoshi Nagata ,  Yasutaka Nakashiba

IPC分类号： H04N314

CPC分类号： H04N5/35581 ,  H01L27/14601 ,  H04N5/374 ,  H04N5/37452

摘要： The image sensor of the present invention performs two exposures of differing exposure times, holds the signal charge that is generated in photodiode 1 in the first exposure period in pixel interior capacitance 4 that is provided inside pixels and integrates the signal charge that is generated in photodiode 1 in the second exposure period with the first signal charge inside the pixels and executes readout, whereby the white (overexposed) portions that occur in the first exposure period are compensated by information of the second exposure period, and black (underexposed) portions that occur in the second exposure period are compensated by information of the first exposure period, and an image is obtained having wide dynamic range with respect to the amount of light in which underexposure and overexposure are mitigated.

公开(公告)号：US07211875B2

公开(公告)日：2007-05-01

申请号：US10819123

申请日：2004-04-07

申请人： Susumu Kurosawa ,  Yuki Fujimoto ,  Yasutaka Nakashiba

发明人： Susumu Kurosawa ,  Yuki Fujimoto ,  Yasutaka Nakashiba

IPC分类号： H01L29/66

CPC分类号： H01L29/94

摘要： An N well is disposed in the upper surface of a P type substrate, a gate insulating film and a gate electrode are disposed thereon, and the gate electrode is connected to a gate terminal. Two p+ diffusion regions are placed in two areas in the surface of the N well sandwiching the gate electrode, and the p+ diffusion regions are connected to a ground potential wiring. Further, an n+ diffusion region is disposed in the surface of the N well, and is connected to a well terminal. Accordingly, capacitance is generated between the gate electrode and the N well of a varactor element. When the potential of the gate terminal is decreased, the two p+ diffusion regions absorb positive holes serving as minority carriers from a channel region.

摘要翻译： 在P型基板的上表面设置有N阱，栅极绝缘膜和栅电极配置在其上，栅电极与栅极端子连接。 两个p + +扩散区被放置在夹入栅电极的N阱表面的两个区域中，并且p + +扩散区连接到地电位布线。 此外，n阱扩散区域设置在N阱的表面中，并且连接到阱端子。 因此，在变容二极管元件的栅电极和N阱之间产生电容。 当栅极端子的电位降低时，两个p + SUP扩散区域从沟道区域吸收用作少数载流子的正空穴。

公开(公告)号：US20060208816A1

公开(公告)日：2006-09-21

申请号：US10566287

申请日：2004-08-03

申请人： Tsuyoshi Ohshima ,  Shigehisa Kurogo ,  Masayuki Ishikawa ,  Susumu Kurosawa ,  Yuki Fujimoto ,  Yasutaka Nakashiba

发明人： Tsuyoshi Ohshima ,  Shigehisa Kurogo ,  Masayuki Ishikawa ,  Susumu Kurosawa ,  Yuki Fujimoto ,  Yasutaka Nakashiba

IPC分类号： H03B5/32

CPC分类号： H01L27/0811 ,  H01L27/0808 ,  H03B5/04 ,  H03B5/366

摘要： Deterioration in frequency stability with time in a conventional piezoelectric oscillator using an accumulation type MOS capacitance element is improved. A P-channel transistor type or an N-channel transistor type is used as a MOS capacitance element in a variable capacitance circuit used in a piezoelectric oscillator. A bias voltage is applied between P-type or N-type extraction electrodes formed in source and drain regions and an N-type extraction electrode provided in an N-well region or a P-type extraction electrode provided in a P-well region. Instability in the MOS capacitance element with time is thus eliminated.

摘要翻译： 在使用积聚型MOS电容元件的传统压电振荡器中频率稳定性随着时间的劣化得到改善。 在压电振荡器中使用的可变电容电路中，使用P沟道晶体管或N沟道晶体管型作为MOS电容元件。 在源极和漏极区域中形成的P型或N型引出电极之间施加偏压，设置在设置在P阱区域的N阱区域或P型引出电极中的N型引出电极。 因此消除了具有时间的MOS电容元件的不稳定性。

公开(公告)号：US07439819B2

公开(公告)日：2008-10-21

申请号：US10566287

申请日：2004-08-03

申请人： Tsuyoshi Ohshima ,  Shigehisa Kurogo ,  Masayuki Ishikawa ,  Susumu Kurosawa ,  Yuki Fujimoto ,  Yasutaka Nakashiba

发明人： Tsuyoshi Ohshima ,  Shigehisa Kurogo ,  Masayuki Ishikawa ,  Susumu Kurosawa ,  Yuki Fujimoto ,  Yasutaka Nakashiba

IPC分类号： H03B5/32 ,  H03B5/12

CPC分类号： H01L27/0811 ,  H01L27/0808 ,  H03B5/04 ,  H03B5/366

摘要： Deterioration in frequency stability with time in a conventional piezoelectric oscillator using an accumulation type MOS capacitance element is improved. A P-channel transistor type or an N-channel transistor type is used as a MOS capacitance element in a variable capacitance circuit used in a piezoelectric oscillator. A bias voltage is applied between P-type or N-type extraction electrodes formed in source and drain regions and an N-type extraction electrode provided in an N-well region or a P-type extraction electrode provided in a P-well region. Instability in the MOS capacitance element with time is thus eliminated.

摘要翻译： 在使用积聚型MOS电容元件的传统压电振荡器中频率稳定性随着时间的劣化得到改善。 在压电振荡器中使用的可变电容电路中，使用P沟道晶体管或N沟道晶体管型作为MOS电容元件。 在源极和漏极区域中形成的P型或N型引出电极之间施加偏压，设置在设置在P阱区域的N阱区域或P型引出电极中的N型引出电极。 因此消除了具有时间的MOS电容元件的不稳定性。

公开(公告)号：US06667468B2

公开(公告)日：2003-12-23

申请号：US09865527

申请日：2001-05-29

申请人： Susumu Kurosawa ,  Yoshinori Muramatsu

发明人： Susumu Kurosawa ,  Yoshinori Muramatsu

IPC分类号： H01L2700

CPC分类号： H04N5/361 ,  H01L27/14609 ,  H04N5/374

摘要： There is disclosed a black-level signal generation circuit for use with a CMOS-based active pixel image sensor. This black-level signal generation circuit delivers a black-level signal of a constant level at all times. The black-level signal generation circuit is equivalent in circuit configuration to any one of pixels forming an effective pixel array and any one of readout portions for reading out signals from the pixels. A photodiode is maintained in a reset state. MOS transistors whose corresponding MOS transistors are turned ‘ON/OFF’ in any one of the pixels and any one of the readout portions are all kept in ‘ON’ state. Thus, the black-level signal generation circuit can constantly produce a black-level signal equivalent in level to the pixel signal delivered when no light is incident on the effective pixels.

摘要翻译： 公开了一种与CMOS基有源像素图像传感器一起使用的黑电平信号发生电路。 该黑电平信号发生电路始终提供恒定电平的黑电平信号。 黑电平信号产生电路在电路配置中等同于形成有效像素阵列的任何一个像素和用于从像素读出信号的读出部分中的任何一个。 光电二极管保持在复位状态。 任何一个像素和任何一个读出部分中的相应的MOS晶体管的“ON / OFF”的MOS晶体管都保持在“ON”状态。 因此，黑电平信号发生电路可以不间断地产生与没有光入射在有效像素上时传送的像素信号相当的黑电平信号。

公开(公告)号：US06667767B1

公开(公告)日：2003-12-23

申请号：US09362220

申请日：1999-07-28

申请人： Yoshinori Muramatsu ,  Susumu Kurosawa

发明人： Yoshinori Muramatsu ,  Susumu Kurosawa

IPC分类号： H04N964

CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H04N5/363 ,  H04N5/3742 ,  H04N5/378

摘要： There is disclosed an image sensor wherein the dispersion in threshold voltages of a transistor constituting a source follower for outputting a signal is compensated. The disclosed image sensor is provided with a coupling capacitor to which an output voltage of a pixel is applied through a transistor and with a transistor of a source follower to read out a voltage at the node S/Hn of the coupling capacitor. The image sensor is so configured that a drain of a transistor is used as a power supply voltage and the transistor is turned on, causing a node S/Hn pre-charged to the power supply voltage, and then the transistor is turned on, causing the voltage of the node S/Hn to be clamped on a sum of a definite voltage and a threshold voltage of the transistor, and further the transistor is turned on, causing an output voltage generated when a pixel is exposed to light to be added to the capacitor, and by restoring the transistor to a power supply voltage of the drain and by again turning the transistor on, an output voltage generated when a pixel is unexposed to light is applied to the capacitor.

摘要翻译： 公开了一种图像传感器，其中补偿了构成用于输出信号的源极跟随器的晶体管的阈值电压的偏差。 所公开的图像传感器设置有耦合电容器，通过晶体管和源极跟随器的晶体管将像素的输出电压施加到耦合电容器，以读出耦合电容器的节点S / Hn处的电压。 图像传感器被配置为使得晶体管的漏极用作电源电压并且晶体管导通，导致预充电到电源电压的节点S / Hn，然后晶体管导通，导致 要钳位在晶体管的定电压和阈值电压之和的节点S / Hn的电压，并且晶体管导通，导致当像素暴露于光时产生的输出电压被添加到 电容器，并且通过将晶体管恢复到漏极的电源电压，并且通过再次使晶体管导通，当将像素未曝光时产生的输出电压施加到电容器。

公开(公告)号：US06999296B2

公开(公告)日：2006-02-14

申请号：US10767105

申请日：2004-01-29

申请人： Susumu Kurosawa ,  Yuki Fujimoto

发明人： Susumu Kurosawa ,  Yuki Fujimoto

IPC分类号： H01G5/01 ,  H01G7/00

CPC分类号： H01L27/0808 ,  H01L27/0811

摘要： A P type substrate is provided on a surface thereof with varactor elements. The varactor element has an N well formed on the surface of the P type substrate, and a gate insulating film is formed on the N well, with a polysilicon layer formed further thereon. On the other hand, the varactor element has an N well formed on the surface of the P type substrate, and a gate insulating film, greater than the gate insulating film in thickness, is formed on the N well. The polysilicon layer is then formed on the gate insulating film. Furthermore, the polysilicon layer is connected to a gate terminal, while the N well is connected to an S/D terminal via N+ diffusion layers.

摘要翻译： 在其表面上设置有可变电抗器元件的P型基板。 可变电抗器元件在P型衬底的表面上形成有N阱，并且在N阱上形成栅极绝缘膜，其中进一步形成多晶硅层。 另一方面，可变电抗器元件在P型衬底的表面上形成有N阱，并且在N阱上形成大于栅极绝缘膜厚度的栅极绝缘膜。 然后在栅极绝缘膜上形成多晶硅层。 此外，多晶硅层连接到栅极端子，而N阱通过N + +扩散层连接到S / D端子。

公开(公告)号：US06208171B1

公开(公告)日：2001-03-27

申请号：US09294089

申请日：1999-04-19

申请人： Kouichi Kumagai ,  Susumu Kurosawa

发明人： Kouichi Kumagai ,  Susumu Kurosawa

IPC分类号： H03K1920

CPC分类号： H03K19/0016

摘要： In a semiconductor integrated circuit, a control transistor 4 and a potential clamp circuit 9 are arranged between a power supply line 2 and a virtual power supply line 3. Even in a sleeve mode where the control transistor 4 is turned off, the potential clamp circuit 9-1 clamps the virtual power supply line 3 at a certain potential to hold a potential state (high level or low level) of each node of a logical circuit. At this time, each FET forming the logical circuit is applied with a back bias so that a threshold voltage Vt becomes higher than that in an active mode. Therefore, a leakage current can be decreased. In the semiconductor integrated circuit, the threshold voltage Vt of the control transistor 4 can be selected to be equal to that of one FET of the complementary FET forming the logical circuit. Therefore, the layout area and the number of manufacturing steps can be reduced.

摘要翻译： 在半导体集成电路中，控制晶体管4和电位钳位电路9配置在电源线2和虚拟电源线3之间。即使在控制晶体管4截止的套管模式中，电位钳位电路 9-1将虚拟电源线3夹在一定电位以保持逻辑电路的每个节点的电位状态（高电平或低电平）。 此时，形成逻辑电路的每个FET被施加反偏压，使得阈值电压Vt变得高于活动模式中的阈值电压。 因此，可以降低泄漏电流。 在半导体集成电路中，可以选择控制晶体管4的阈值电压Vt等于形成逻辑电路的互补FET的一个FET的阈值电压Vt。 因此，可以减少布局区域和制造步骤的数量。

公开(公告)号：US5748016A

公开(公告)日：1998-05-05

申请号：US618778

申请日：1996-03-20

申请人： Susumu Kurosawa

发明人： Susumu Kurosawa

IPC分类号： H03K17/567 ,  H01L29/786 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/0185

CPC分类号： H03K19/0013 ,  H01L29/78606 ,  H03K19/00361 ,  H03K2217/0018

摘要： A driver circuit comprising (i) a pair of complementary MOS (CMOS) transistors connected in series and receiving an identical input signal, and (ii) a pair of control transistors changing a threshold voltage state of each of the pair of CMOS transistors by applying a plurality of voltages to a body terminal of each of the pair of CMOS transistors depending upon the ON/OFF state of each of the pair of CMOS transistors. Such a driver circuit is capable of reconciling a high-speed operation with a low power consumption under low power supply voltage conditions.

摘要翻译： 一种驱动器电路，包括：（i）串联连接并接收相同输入信号的一对互补MOS（CMOS）晶体管，以及（ii）一对控制晶体管，其通过施加来改变所述一对CMOS晶体管的阈值电压状态 根据所述一对CMOS晶体管中的每一个的ON / OFF状态，对所述一对CMOS晶体管的每一个的体电极进行多个电压。 这样的驱动器电路能够在低电源电压条件下使高速操作与低功耗协调。