公开(公告)号：US06518835B2

公开(公告)日：2003-02-11

申请号：US10142897

申请日：2002-05-13

申请人： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

发明人： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

IPC分类号： H01L2500

CPC分类号： H01L23/5222 ,  H01L23/50 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

摘要翻译： 一种半导体集成电路器件，包括：第一互连沟道，包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层;第二互连沟道，包括多个第三层金属互连层， 第二方向垂直于第一方向;内部电源电路，其接收从外部端子提供的源极电压并产生与源极电压不同的电压，并且设置有稳定电容器，形成大部分稳定化电容器 在第二和第三层金属互连线彼此相交的区域中。

公开(公告)号：US06411160B1

公开(公告)日：2002-06-25

申请号：US09376470

申请日：1999-08-18

申请人： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

发明人： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

IPC分类号： H01L2500

CPC分类号： H01L23/5222 ,  H01L23/50 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.

摘要翻译： 在一种半导体集成电路器件中，包括第一互连通道，第一互连通道包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层，第二互连通道，包括在第二互连层中延伸的多个第三层金属互连层 内部电源电路，其接收从外部端子提供的源极电压，并产生与源极电压不同的电压，并且设置有稳定电容器，大部分稳定化电容器处于 第二和第三层金属互连线彼此相交的区域。

公开(公告)号：US06707139B2

公开(公告)日：2004-03-16

申请号：US09928497

申请日：2001-08-14

申请人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

发明人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

IPC分类号： H01L2348

CPC分类号： H01L27/10897 ,  G11C5/025 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

摘要翻译： 具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。 在每个单位区域上形成沿第一方向延伸的第一互连。 沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。 在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。 根据需要，在每个单位区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式。

公开(公告)号：US06274895B1

公开(公告)日：2001-08-14

申请号：US09385631

申请日：1999-08-27

申请人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

发明人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

IPC分类号： H01L2710

CPC分类号： H01L27/10897 ,  G11C5/025 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.

摘要翻译： 具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。 在每个单位区域上形成沿第一方向延伸的第一互连。 沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。 在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。 在每个单元区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式，根据需要，根据与其相邻的布线专用区域的组合。

公开(公告)号：US07710142B2

公开(公告)日：2010-05-04

申请号：US12323075

申请日：2008-11-25

申请人： Ryo Hirano ,  Yukihide Suzuki ,  Hidekazu Egawa

发明人： Ryo Hirano ,  Yukihide Suzuki ,  Hidekazu Egawa

IPC分类号： G01R31/02 ,  G01R31/28

CPC分类号： G01R31/31721 ,  G01R31/2884 ,  G01R31/3172 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/5602 ,  Y10T307/858

摘要： A semiconductor integrated circuit includes power supply pads of two or more kinds, switches each of which is connected between adjacent two of the power supply pads to allow short-circuiting them, and at least one control line connected to control terminals of the switches according to the kinds of the power supply pads connected to the switches.

摘要翻译： 半导体集成电路包括两个或更多种类型的电源焊盘，每个电源焊盘连接在相邻的两个电源焊盘之间以允许它们短路，并且至少一个控制线连接到开关的控制端，根据 连接到开关的电源垫的种类。

公开(公告)号：US08451676B2

公开(公告)日：2013-05-28

申请号：US12605688

申请日：2009-10-26

申请人： Hidekazu Egawa

发明人： Hidekazu Egawa

IPC分类号： G11C7/02

CPC分类号： G11C7/02

摘要： A semiconductor device may include, but is not limited to, a first signal line, a second signal line, and a first shield line. The first signal line is supplied with a first signal. The first signal is smaller in amplitude than a potential difference between a power potential and a reference potential. The second signal line is disposed in a first side of the first signal line. The second signal line is supplied with a second signal. The second signal is smaller in amplitude than the potential difference. The first shield line is disposed in a second side of the first signal line. The second side is opposite to the first side. The first shield line reduces a coupling noise that is applied to the first shield line from the second side.

摘要翻译： 半导体器件可以包括但不限于第一信号线，第二信号线和第一屏蔽线。 第一信号线被提供有第一信号。 第一信号的振幅小于功率电位和参考电位之间的电位差。 第二信号线设置在第一信号线的第一侧。 第二信号线被提供有第二信号。 第二信号的振幅小于电位差。 第一屏蔽线设置在第一信号线的第二侧。 第二面与第一面相反。 第一屏蔽线减少了从第二侧施加到第一屏蔽线的耦合噪声。

公开(公告)号：US09443573B2

公开(公告)日：2016-09-13

申请号：US14504045

申请日：2014-10-01

申请人： Hidekazu Egawa

发明人： Hidekazu Egawa

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4096

CPC分类号： G11C11/4091 ,  G11C5/02 ,  G11C5/025 ,  G11C7/065 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4096

摘要： A semiconductor device includes a plurality of main amplifiers provided between memory cell arrays. One of the main amplifiers is disposed closer to one of the memory cell arrays than to the other of memory cell arrays, and the other of the main amplifiers is disposed closer to the other of the memory cell arrays than to the one of the memory cell arrays. Additional apparatus are disclosed.

摘要翻译： 半导体器件包括设置在存储单元阵列之间的多个主放大器。 主放大器中的一个被放置得比存储单元阵列中的另一个更靠近存储单元阵列之一，并且另一个主放大器被设置成比存储单元中的一个更靠近存储单元阵列中的另一个 阵列 公开了附加装置。

公开(公告)号：US20110065249A1

公开(公告)日：2011-03-17

申请号：US12805016

申请日：2010-07-07

申请人： Hidekazu Egawa

发明人： Hidekazu Egawa

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/1037 ,  H01L29/66181 ,  H01L29/78

摘要： A method of manufacturing a semiconductor device includes: performing, in a case of manufacturing a first semiconductor device which operates by a first power supply voltage, at least one step from among channel ion implantation, gate oxide film formation, and gate electrode patterning according to a process of forming an element which operates with the first power supply voltage; performing, in a case of manufacturing a second semiconductor device which operates by a second power supply voltage, at least one step from among the channel ion implantation, the gate oxide film formation, and the gate electrode patterning according to a process of forming an element which operates with the second power supply voltage; and commonly performing at least diffusion region formation in the case of manufacturing the first semiconductor device and in the case of manufacturing the second semiconductor device.

摘要翻译： 一种制造半导体器件的方法包括：在制造通过第一电源电压工作的第一半导体器件的情况下，进行从沟道离子注入，栅极氧化膜形成和栅极电极图案化的至少一个步骤，根据 形成以第一电源电压工作的元件的工艺; 在制造通过第二电源电压工作的第二半导体器件的情况下，根据形成元件的工艺，从通道离子注入，栅极氧化膜形成和栅极电极图案化中至少一个步骤 其工作与第二电源电压; 并且在制造第一半导体器件的情况下和在制造第二半导体器件的情况下通常执行至少扩散区域形成。