公开(公告)号：US06518835B2

公开(公告)日：2003-02-11

申请号：US10142897

申请日：2002-05-13

申请人： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

发明人： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

IPC分类号： H01L2500

CPC分类号： H01L23/5222 ,  H01L23/50 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

摘要翻译： 一种半导体集成电路器件，包括：第一互连沟道，包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层;第二互连沟道，包括多个第三层金属互连层， 第二方向垂直于第一方向;内部电源电路，其接收从外部端子提供的源极电压并产生与源极电压不同的电压，并且设置有稳定电容器，形成大部分稳定化电容器 在第二和第三层金属互连线彼此相交的区域中。

公开(公告)号：US06411160B1

公开(公告)日：2002-06-25

申请号：US09376470

申请日：1999-08-18

申请人： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

发明人： Yoshiro Riho ,  Kiyoshi Nakai ,  Hidekazu Egawa ,  Yukihide Suzuki ,  Isamu Fujii

IPC分类号： H01L2500

CPC分类号： H01L23/5222 ,  H01L23/50 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.

摘要翻译： 在一种半导体集成电路器件中，包括第一互连通道，第一互连通道包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层，第二互连通道，包括在第二互连层中延伸的多个第三层金属互连层 内部电源电路，其接收从外部端子提供的源极电压，并产生与源极电压不同的电压，并且设置有稳定电容器，大部分稳定化电容器处于 第二和第三层金属互连线彼此相交的区域。

公开(公告)号：US06707139B2

公开(公告)日：2004-03-16

申请号：US09928497

申请日：2001-08-14

申请人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

发明人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

IPC分类号： H01L2348

CPC分类号： H01L27/10897 ,  G11C5/025 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

摘要翻译： 具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。 在每个单位区域上形成沿第一方向延伸的第一互连。 沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。 在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。 根据需要，在每个单位区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式。

公开(公告)号：US06274895B1

公开(公告)日：2001-08-14

申请号：US09385631

申请日：1999-08-27

申请人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

发明人： Isamu Fujii ,  Kiyoshi Nakai ,  Yukihide Suzuki ,  Sadayuki Morita ,  Hidekazu Egawa ,  Katura Abe ,  Noriaki Sakamoto

IPC分类号： H01L2710

CPC分类号： H01L27/10897 ,  G11C5/025 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.

摘要翻译： 具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。 在每个单位区域上形成沿第一方向延伸的第一互连。 沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。 在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。 在每个单元区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式，根据需要，根据与其相邻的布线专用区域的组合。

公开(公告)号：US5557580A

公开(公告)日：1996-09-17

申请号：US292452

申请日：1994-08-18

申请人： Shigeki Numaga ,  Shunichi Sukegawa ,  Takashi Inui ,  Yukihide Suzuki ,  Kiyoshi Nakai

发明人： Shigeki Numaga ,  Shunichi Sukegawa ,  Takashi Inui ,  Yukihide Suzuki ,  Kiyoshi Nakai

IPC分类号： G11C11/407 ,  G11C8/08 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/08

摘要： A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.

摘要翻译： 一种字线驱动电路，通过使字线驱动器的布局面积小，能够有效地防止字线放电期间的接地噪声，同时容纳字线中的音调变窄。 字线驱动电路包括n型MOS晶体管14和p型MOS晶体管12. n型MOS晶体管14的漏极端子和字线驱动器10中的p型MOS晶体管12的漏极端子连接到基极 字线WLi的终端。 输出晶体管驱动电路16的输出端子与p型MOS晶体管12的源极端子连接，第一输出晶体管控制电路18的输出端子与栅极端子连接。 第二输出晶体管控制电路20的输出端子与n型MOS晶体管14的栅极端子连接，作为引导电流的基准电位端子的接地端子22与源极端子连接。

公开(公告)号：US5497349A

公开(公告)日：1996-03-05

申请号：US267025

申请日：1994-06-21

申请人： Kiyoshi Nakai ,  Yukihide Suzuki ,  Takashi Inui

发明人： Kiyoshi Nakai ,  Yukihide Suzuki ,  Takashi Inui

IPC分类号： H01L27/10 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C7/10

摘要： A dynamic random access memory device has a memory cell array which includes a first memory cell array part and a second memory cell array part portioned in a first direction parallel with the bit lines, a plurality of column switches, one provided for each of the bit lines, a plurality of input/output lines each connected to different ones of the bit lines via associated ones of the column switches, a row address decoder for decoding a first portion of an address signal and a column address decoder for decoding a second portion of the address signal to thereby simultaneously access at least two memory cells with the address signal. The input/output lines extend in a second direction parallel with word lines and are divided into first and second groups of input/output lines connected to those bit lines which belong to the first and second memory cell array parts, respectively in which the first input/output line group is isolated from the second input/output line group. A first input/output gate circuit is connected to the first group of input/output lines and a second input/output gate circuit is connected to the second group of input/output lines, in which the first and second input/output gate circuits serve to selectively transfer therethrough, between main amplifiers and the first input/output line groups, data to be simultaneously read from or written into the at least two memory cells in the memory cell array.

摘要翻译： 动态随机存取存储器件具有存储单元阵列，其包括第一存储单元阵列部分和与位线平行的第一方向上分配的第二存储单元阵列部分，多个列开关，每个位开关 线路，多个输入/输出线路，每条线路经由相关联的列开关连接到不同的位线，用于解码地址信号的第一部分的行地址解码器和用于解码第二部分的列地址解码器 由此地址信号由此同时访问具有地址信号的至少两个存储单元。 输入/输出线在与字线平行的第二方向上延伸，并且被分成连接到属于第一和第二存储单元阵列部分的那些位线的第一和第二组输入/输出线，其中第一输入 /输出线路组与第二个输入/输出线组隔离。 第一输入/输出门电路连接到第一组输入/输出线，并且第二输入/输出门电路连接到第二组输入/输出线，其中第一和第二输入/输出门电路服务 以在主放大器和第一输入/输出线组之间选择性地传送数据，以同时从存储单元阵列中的至少两个存储单元中读取或写入数据。

公开(公告)号：US5615156A

公开(公告)日：1997-03-25

申请号：US250130

申请日：1994-05-27

申请人： Hiroyuki Yoshida ,  Takashi Inui ,  Shigeki Numaga ,  Kiyoshi Nakai ,  Yukihide Suzuki

发明人： Hiroyuki Yoshida ,  Takashi Inui ,  Shigeki Numaga ,  Kiyoshi Nakai ,  Yukihide Suzuki

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C29/80

摘要： A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.

摘要翻译： 具有备用位线或字线的半导体存储器件，用于替换有缺陷的位线或字线，这些位线或字线可以增加缺陷消除概率并提高操作余量。 保留位线或字线大致设置在存储垫的中央部分。 由于在备用字线或位线中存在缺陷发生的可能性低的情况，当用保留字线或位线替换缺陷字线或位线时，可能会使缺陷发生的概率变低。

公开(公告)号：US07813178B2

公开(公告)日：2010-10-12

申请号：US12003163

申请日：2007-12-20

申请人： Kiyoshi Nakai

发明人： Kiyoshi Nakai

IPC分类号： G11C11/34

CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2207/2218 ,  G11C2207/2245

摘要： Disclosed is a semiconductor memory device which includes a read data latch that holds read data from a phase change memory and latches write data entered from outside and holds write data entered from outside, a write data latch that holds the write data for a cell for the time duration of a preset number of cycles until start of data write, a transfer switch that controls whether or not an output of the read data latch is to be transferred to the write data latch, a comparator circuit that decides whether or not data transferred to the write data latch via the transfer switch and held in the write data latch and data in the read data latch are coincident with each other, and a write flag latch that latches an output of the comparator circuit. Data is written only in case there is a write request and the result of comparison of the comparator circuit indicates non-coincidence, that is, only in bits in need of data writing.

摘要翻译： 公开了一种半导体存储器件，其包括读取数据锁存器，其保存来自相变存储器的读取数据并锁存从外部输入的写入数据，并保存从外部输入的写入数据;写入数据锁存器， 直到数据写入开始为止的预设数量的周期的持续时间;控制读取数据锁存器的输出是否被传送到写数据锁存器的转移开关;判定数据传送到 通过转换开关写入数据锁存器并保持在写入数据锁存器中，读取数据锁存器中的数据彼此一致，并且写入标志锁存器锁存比较器电路的输出。 只有在存在写请求的情况下才写入数据，并且比较电路的比较结果表示不一致，即仅在需要数据写入的位中。

公开(公告)号：US07742332B2

公开(公告)日：2010-06-22

申请号：US12222953

申请日：2008-08-20

申请人： Kiyoshi Nakai

发明人： Kiyoshi Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/78 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A semiconductor memory device includes: first and second wiring layers extending in substantially parallel to each other in a first direction; a first semiconductor region formed in a part of a portion between the first and second wiring layers; a second semiconductor region formed on an opposite side to the first semiconductor region with respect to the second wiring layer and making a pair with the first semiconductor region; a third semiconductor region formed in another part of the portion between the first and second wiring layers; a fourth semiconductor region formed on an opposite side to the third semiconductor region with respect to the first wiring layer and making a pair with the third semiconductor region; a third wiring layer extending in a second direction that crosses the first direction and having an electrical contact with the first semiconductor region; a fourth wiring layer extending in the second direction and having an electrical contact with the fourth semiconductor region; a fifth wiring layer extending in the first direction to cross over the first and third semiconductor regions.

摘要翻译： 半导体存储器件包括：第一和第二布线层，其在第一方向上彼此基本平行地延伸; 形成在所述第一和第二布线层之间的部分的一部分中的第一半导体区域; 第二半导体区域，相对于所述第二布线层形成在与所述第一半导体区域相反的一侧，并与所述第一半导体区域成对; 形成在第一和第二布线层之间的部分的另一部分中的第三半导体区域; 第四半导体区域，其形成在与所述第三半导体区域相对于所述第一布线层的相反侧并与所述第三半导体区域成对; 第三布线层，沿与所述第一方向交叉的第二方向延伸并与所述第一半导体区域电接触; 第四布线层，沿第二方向延伸并与第四半导体区域电接触; 第五布线层，其沿第一方向延伸以跨过第一和第三半导体区域。

公开(公告)号：US07508707B2

公开(公告)日：2009-03-24

申请号：US12003734

申请日：2007-12-31

申请人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

发明人： Kiyoshi Nakai ,  Kazuhiko Kajigaya ,  Isamu Asano

IPC分类号： G11C14/00

CPC分类号： G11C11/005 ,  G11C7/20 ,  G11C11/4072 ,  G11C13/0004

摘要： Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

摘要翻译： 公开了一种半导体存储装置，其中两种存储器，即易失性存储器和非易失性存储器安装在一个芯片上。 DRAM存储器阵列的数据在进入数据保持模式之前或在断电之前被保存在非易失性存储器的相应区域中，并且数据从非易失性存储器的区域传送到DRAM存储器阵列 数据保留模式或上电。 对DRAM存储器阵列进行正常读/写访问，而数据保留位于非易失性存储器的区域。