公开(公告)号：US09042457B2

公开(公告)日：2015-05-26

申请号：US12673408

申请日：2009-06-05

Applicant: Yoshiteru Hayashi ,  Hiroshi Amano ,  Masayasu Iguchi

Inventor： Yoshiteru Hayashi ,  Hiroshi Amano ,  Masayasu Iguchi

IPC: H04N7/12 ,  H04N19/436 ,  H04N19/176 ,  H04N19/70 ,  H04N19/134 ,  H04N19/61 ,  H04N19/147 ,  H04N19/44 ,  H04N19/13 ,  H04N19/124 ,  H04N19/132 ,  H04N19/40

CPC classification number: H04N19/436 ,  H04N19/124 ,  H04N19/13 ,  H04N19/132 ,  H04N19/134 ,  H04N19/147 ,  H04N19/174 ,  H04N19/176 ,  H04N19/40 ,  H04N19/44 ,  H04N19/61 ,  H04N19/70

Abstract: An image decoding apparatus which decodes, in parallel, a coded stream having processing order dependency includes: a slice data predecoding unit which predecodes, on a macroblock group basis, macroblock groups included in the coded stream to generate macroblock decoding information necessary for decoding other macroblock groups; and a first macroblock decoding unit and a second macroblock decoding unit each of which decodes a corresponding one of macroblock groups included in the coded stream in parallel. Each of the macroblock decoding units, when decoding the corresponding one of macroblock groups, uses the macroblock decoding information that has been generated for the other macroblock group.

Abstract translation: 并行解码具有处理顺序依赖性的编码流的图像解码装置包括：切片数据预解码单元，其以宏块组为基础对包含在编码流中的宏块组进行预解码，以生成解码其他宏块所需的宏块解码信息 团体 以及第一宏块解码单元和第二宏块解码单元，每个解码单元并行地解码编码流中包括的宏块组中的对应的一个。 每个宏块解码单元在对宏块组中相应的一个进行解码时，使用为其他宏块组生成的宏块解码信息。

公开(公告)号：US20110200115A1

公开(公告)日：2011-08-18

申请号：US12673408

申请日：2009-06-05

Applicant: Yoshiteru Hayashi ,  Hiroshi Amano ,  Masayasu Iguchi

Inventor： Yoshiteru Hayashi ,  Hiroshi Amano ,  Masayasu Iguchi

IPC: H04N7/26

CPC classification number: H04N19/436 ,  H04N19/124 ,  H04N19/13 ,  H04N19/132 ,  H04N19/134 ,  H04N19/147 ,  H04N19/174 ,  H04N19/176 ,  H04N19/40 ,  H04N19/44 ,  H04N19/61 ,  H04N19/70

Abstract: An image decoding apparatus (40) which decodes, in parallel, a coded stream (Str) having processing order dependency includes: a slice data predecoding unit (402) which predecodes, on a macroblock group basis, macroblock groups included in the coded stream (Str) to generate macroblock decoding information (1001) necessary for decoding other macroblock groups; and a first macroblock decoding unit (404) and a second macroblock decoding unit (405) each of which decodes a corresponding one of macroblock groups included in the coded stream (Str) in parallel. Each of the macroblock decoding units (404, 405), when decoding the corresponding one of macroblock groups, uses the macroblock decoding information (1001) that has been generated for the other macroblock group.

Abstract translation: 并行地解码具有处理顺序依赖性的编码流（Str）的图像解码装置（40）包括：切片数据预解码单元（402），其以宏块组为基础对包含在编码流中的宏块组 Str）生成对其他宏块组进行解码所需的宏块解码信息（1001） 以及第一宏块解码单元（404）和第二宏块解码单元（405），每个宏块解码单元并行地解码编码流（Str）中包括的宏块组中的对应的一个。 每个宏块解码单元（404,405）在对宏块组中相应的一个进行解码时，使用为其他宏块组生成的宏块解码信息（1001）。

公开(公告)号：US20120051433A1

公开(公告)日：2012-03-01

申请号：US13292543

申请日：2011-11-09

Applicant: Mikiko Roji ,  Masayasu Iguchi ,  Kotaro Esaki ,  Hiroshi Amano

Inventor： Mikiko Roji ,  Masayasu Iguchi ,  Kotaro Esaki ,  Hiroshi Amano

IPC: H04N7/32

CPC classification number: H04N19/61

Abstract: While temporal and spatial direct modes are both supported, the amount of temporarily-stored direct-mode prediction information is reduced, thereby reducing the memory bus bandwidth. A motion information generator combines a motion vector for an anchor block with the number of a reference picture of the anchor block, thereby generates motion information of the pixel block. A still-state determination unit determines whether or not the pixel block is considered still based on the motion vector for the anchor block and on the number of the reference picture. A selector selectively stores in a memory either an output of the motion information generator or a determination result of the still-state determination unit as direct-mode prediction information of the pixel block. A motion vector predictor predicts a motion vector for the pixel block in direct mode based on the direct-mode prediction information stored in the memory.

Abstract translation: 虽然都支持时间和空间直接模式，但是减少临时存储的直接模式预测信息的量，从而减少存储器总线带宽。 运动信息生成器将锚块的运动矢量与锚块的参考图像的数量组合，从而生成像素块的运动信息。 静止状态确定单元基于锚块的运动矢量和参考图像的数量来确定是否仍然考虑像素块。 选择器选择性地将运动信息发生器的输出或静止状态确定单元的确定结果存储在存储器中作为像素块的直接模式预测信息。 运动矢量预测器基于存储在存储器中的直接模式预测信息，以直接模式预测像素块的运动矢量。

公开(公告)号：US20090110077A1

公开(公告)日：2009-04-30

申请号：US12301630

申请日：2007-05-23

Applicant: Hiroshi Amano ,  Takeshi Tanaka ,  Masaki Maeda ,  Kenjiro Tsuda ,  Masayasu Iguchi ,  Youji Shibahara

Inventor： Hiroshi Amano ,  Takeshi Tanaka ,  Masaki Maeda ,  Kenjiro Tsuda ,  Masayasu Iguchi ,  Youji Shibahara

IPC: H04N7/32 ,  H04N7/26

CPC classification number: H04N19/139 ,  H04N19/105 ,  H04N19/109 ,  H04N19/137 ,  H04N19/176 ,  H04N19/43 ,  H04N19/436 ,  H04N19/51 ,  H04N19/52 ,  H04N19/61

Abstract: When compression encoding processing of an image is performed in units of macroblocks using pipeline structure, application of the skip mode or the like according to MPEG4AVC to compression encode an encoding target block requires motion vectors and the like of adjacent blocks of the encoding target block. However, depending on the structure of the pipeline stages, the motion vectors and the like may not be determined. In such cases, the skip mode cannot be applied to compression encode the encoding target block. The present invention aims to solve this problem and (i) calculates all motion information candidates, of the encoding target block, corresponding to all motion information selectable by a previous block of the encoding target block, and (ii) selects, as the motion information of the encoding target block in the skip mode, the motion information corresponding to the motion information determined for the previous block.

Abstract translation: 当使用流水线结构以宏块为单位执行图像的压缩编码处理时，根据MPEG4AVC的跳过模式等的应用对编码对象块进行压缩编码需要编码对象块的相邻块的运动矢量等。 然而，根据流水线级的结构，可能不能确定运动矢量等。 在这种情况下，跳过模式不能应用于编码目标块的压缩编码。 本发明旨在解决这个问题，（i）计算编码目标块的所有运动信息候选，对应于由编码目标块的先前块选择的所有运动信息，以及（ii）选择运动信息 在所述跳过模式中的所述编码对象块的所述运动信息对应于针对所述前一块确定的运动信息。

公开(公告)号：US08897583B2

公开(公告)日：2014-11-25

申请号：US12669591

申请日：2009-05-21

Applicant: Hiroshi Amano ,  Masayasu Iguchi

Inventor： Hiroshi Amano ,  Masayasu Iguchi

IPC: G06K9/36 ,  H04N19/44 ,  H04N19/61 ,  H04N19/436 ,  H04N19/55 ,  H04N19/176

CPC classification number: H04N19/177 ,  H04N19/107 ,  H04N19/176 ,  H04N19/436 ,  H04N19/44 ,  H04N19/55 ,  H04N19/61 ,  H04N19/85

Abstract: To provide an image decoding apparatus that suppresses overhead of parallel processing to improve parallelization efficiency and reduce circuit costs, while solving neighboring macroblock dependencies. The image decoding apparatus (100) includes first and second decoding circuits (101, 102) having a transfer unit that transfers right neighborhood information or left neighborhood information, and first and second transfer completion detection units (104, 105) that respectively detect whether or not the left neighborhood information or the right neighborhood information has been transferred to the first and second decoding circuits (101, 102). Each of the first and second decoding circuits (101, 102) decodes a decoding target macroblock positioned at an edge of a region, when the transfer of the left neighborhood information or the right neighborhood information is detected. A boundary line between regions is orthogonal to a decoding direction corresponding to an order in which macroblocks adjacent to each other are sequentially decoded.

Abstract translation: 提供抑制并行处理的开销以提高并行化效率并降低电路成本的图像解码装置，同时解决相邻的宏块依赖性。 图像解码装置（100）包括具有传送右邻域信息或左邻域信息的传送单元的第一和第二解码电路（101,102），以及第一和第二传送完成检测单元（104,105），其分别检测是否 不是左邻域信息或右邻域信息已被传送到第一和第二解码电路（101,102）。 当检测到左邻居信息或右邻域信息的传送时，第一和第二解码电路（101,102）中的每一个解码位于区域边缘的解码目标宏块。 区域之间的边界线与对应于彼此相邻的宏块顺序解码的顺序的解码方向正交。

公开(公告)号：US20100195922A1

公开(公告)日：2010-08-05

申请号：US12669591

申请日：2009-05-21

Applicant: Hiroshi Amano ,  Masayasu Iguchi

Inventor： Hiroshi Amano ,  Masayasu Iguchi

IPC: G06K9/36

CPC classification number: H04N19/177 ,  H04N19/107 ,  H04N19/176 ,  H04N19/436 ,  H04N19/44 ,  H04N19/55 ,  H04N19/61 ,  H04N19/85

Abstract: To provide an image decoding apparatus that suppresses overhead of parallel processing to improve parallelization efficiency and reduce circuit costs, while solving neighboring macroblock dependencies. The image decoding apparatus (100) includes first and second decoding circuits (101, 102) having a transfer unit that transfers right neighborhood information or left neighborhood information, and first and second transfer completion detection units (104, 105) that respectively detect whether or not the left neighborhood information or the right neighborhood information has been transferred to the first and second decoding circuits (101, 102). Each of the first and second decoding circuits (101, 102) decodes a decoding target macroblock positioned at an edge of a region, when the transfer of the left neighborhood information or the right neighborhood information is detected. A boundary line between regions is orthogonal to a decoding direction corresponding to an order in which macroblocks adjacent to each other are sequentially decoded.

Abstract translation: 提供抑制并行处理的开销以提高并行化效率并降低电路成本的图像解码装置，同时解决相邻的宏块依赖性。 图像解码装置（100）包括具有传送右邻域信息或左邻域信息的传送单元的第一和第二解码电路（101,102），以及第一和第二传送完成检测单元（104,105），其分别检测是否 不是左邻域信息或右邻域信息已被传送到第一和第二解码电路（101,102）。 当检测到左邻居信息或右邻域信息的传送时，第一和第二解码电路（101,102）中的每一个解码位于区域边缘的解码目标宏块。 区域之间的边界线与对应于彼此相邻的宏块顺序解码的顺序的解码方向正交。

公开(公告)号：US10033997B2

公开(公告)日：2018-07-24

申请号：US13805704

申请日：2011-06-21

Applicant: Yoshiteru Hayashi ,  Takeshi Tanaka ,  Takashi Hashimoto ,  Satoshi Kajita ,  Hiroshi Amano

Inventor： Yoshiteru Hayashi ,  Takeshi Tanaka ,  Takashi Hashimoto ,  Satoshi Kajita ,  Hiroshi Amano

IPC: H04N7/32 ,  H04N19/50 ,  H04N19/51 ,  H04N19/44 ,  H04N19/52 ,  H04N19/176 ,  H04N19/61 ,  H04N19/96 ,  H04N19/107 ,  H04N19/86

Abstract: An image decoding device is provided that decodes, without an increase in the circuit size, a coded video sequence including a large-size block. The image decoding apparatus includes: a block division unit which divides a current block that is to be decoded and is included in a picture of the coded video sequence, into sub-blocks; an image obtainment unit which obtains, for each of the sub-blocks, image data corresponding to the sub-block from a recording medium; a prediction unit which generates, for each of the sub-blocks, a predicted image of the sub-block, based on the image data obtained by the image obtainment unit; and a reconstruction unit which reconstructs each of the sub-blocks, by adding the predicted image generated for the sub-block to the sub-block.

公开(公告)号：US08559736B2

公开(公告)日：2013-10-15

申请号：US13321857

申请日：2011-03-16

Applicant: Hiroshi Amano ,  Takeshi Tanaka ,  Takashi Hashimoto ,  Yoshiteru Hayashi

Inventor： Hiroshi Amano ,  Takeshi Tanaka ,  Takashi Hashimoto ,  Yoshiteru Hayashi

IPC: H04N7/50

CPC classification number: H04N19/60 ,  H04N19/122 ,  H04N19/44 ,  H04N19/547

Abstract: A decoding apparatus (100) according to the present invention includes: a decoding unit (101) which decodes identification information identifying an orthogonal transform basis for inverse orthogonal transform; an orthogonal transform basis accumulation unit (110) accumulating orthogonal transform bases for inverse orthogonal transform; an orthogonal transform basis storage unit (103) storing an orthogonal transform basis for inverse transform, from among the stored orthogonal transform bases; an inverse orthogonal transform unit (112) which performs inverse orthogonal transform using the identified orthogonal transform basis; and an orthogonal transform basis transfer control unit (102) which transfers the identified orthogonal transfer basis from the orthogonal transform basis accumulation unit (110) to the orthogonal transfer basis storage unit (103) only when the identified orthogonal transform basis is not yet stored therein. With this structure, it is possible to reduce the memory bandwidth for the memory storing the orthogonal transform basis and the memory access latency.

Abstract translation: 根据本发明的解码装置（100）包括：解码单元（101），其对识别用于逆正交变换的正交变换基准的识别信息进行解码; 正交变换基积累单元（110），累积用于逆正交变换的正交变换基; 正交变换基准存储单元，从存储的正交变换基中存储用于逆变换的正交变换基础; 使用所识别的正交变换基础进行逆正交变换的逆正交变换单元（112） 以及正交变换基传送控制单元（102），其仅在所识别的正交变换基础尚未存储时，将所识别的正交传送基础从正交变换基础累积单元（110）传送到正交传送基础存储单元（103） 。 利用这种结构，可以减少存储正交变换基础和存储器访问延迟的存储器的存储器带宽。

公开(公告)号：US20110235716A1

公开(公告)日：2011-09-29

申请号：US13121041

申请日：2010-10-07

Applicant: Takeshi Tanaka ,  Hiroshi Amano ,  Yoshiteru Hayashi ,  Takashi Hashimoto ,  Satoshi Kajita

Inventor： Takeshi Tanaka ,  Hiroshi Amano ,  Yoshiteru Hayashi ,  Takashi Hashimoto ,  Satoshi Kajita

IPC: H04N7/26

CPC classification number: H04N19/433 ,  H04N19/44

Abstract: A decoding apparatus (100) includes: a first memory unit (20) storing pixel data of a decoded reference image to be referred to in decoding; a second memory unit (30) having a storage capacity smaller than that of the first memory unit (20) and providing a data reading speed faster than that provided by the first memory unit (20); a search area transfer unit (40) transferring, from the first memory unit (20) to the second memory unit (30), pixel data in a search area that is a part of the reference image and required to calculate a motion vector for the block; a motion vector operating unit (50) calculating the motion vector by repeatedly (i) reading out, from the second memory unit (30), the pixel data and (ii) performing a predetermined operation on the pixel data; and a decoding unit (60) decoding the block using the calculated motion vector.

Abstract translation: 解码装置（100）包括：第一存储单元，存储解码中要参考的解码参考图像的像素数据; 具有比第一存储单元（20）的存储容量小的存储容量的第二存储器单元（30），并且提供比由第一存储器单元（20）提供的数据读取速度更快的数据读取速度; 搜索区域传送单元，从第一存储单元（20）向第二存储单元（30）传送作为参考图像的一部分的搜索区域中的像素数据，并且需要计算用于 块; 运动矢量运算单元，通过重复地（i）从第二存储器单元（30）读出像素数据和（ii）对像素数据执行预定的操作来计算运动矢量; 以及解码单元（60），使用所计算的运动矢量对该块进行解码。

公开(公告)号：US20130089149A1

公开(公告)日：2013-04-11

申请号：US13805704

申请日：2011-06-21

Applicant: Yoshiteru Hayashi ,  Takeshi Tanaka ,  Takashi Hashimoto ,  Satoshi Kajita ,  Hiroshi Amano

Inventor： Yoshiteru Hayashi ,  Takeshi Tanaka ,  Takashi Hashimoto ,  Satoshi Kajita ,  Hiroshi Amano

IPC: H04N7/32

CPC classification number: H04N19/51 ,  H04N19/107 ,  H04N19/176 ,  H04N19/44 ,  H04N19/52 ,  H04N19/61 ,  H04N19/86 ,  H04N19/96

Abstract: An image decoding device is provided that decodes, without an increase in the circuit size, a coded video sequence including a large-size block. The image decoding apparatus includes: a block division unit which divides a current block that is to be decoded and is included in a picture of the coded video sequence, into sub-blocks; an image obtainment unit which obtains, for each of the sub-blocks, image data corresponding to the sub-block from a recording medium; a prediction unit which generates, for each of the sub-blocks, a predicted image of the sub-block, based on the image data obtained by the image obtainment unit; and a reconstruction unit which reconstructs each of the sub-blocks, by adding the predicted image generated for the sub-block to the sub-block.

Abstract translation: 提供了一种图像解码装置，其不增加电路尺寸，对包括大尺寸块的编码视频序列进行解码。 图像解码装置包括：块分割单元，将要被解码并被包括在编码视频序列的图像中的当前块划分成子块; 对于每个子块，从记录介质获取与子块相对应的图像数据的图像获取单元; 基于由所述图像获取单元获得的图像数据，对于每个所述子块生成所述子块的预测图像的预测单元; 以及重建单元，通过将对于子块生成的预测图像添加到子块中，来重构每个子块。