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公开(公告)号：US20130155749A1
公开(公告)日：2013-06-20
申请号：US13770436
申请日：2013-02-19
申请人： Young Seog KIM , Kuoyuan HSU , Jacklyn CHANG
发明人： Young Seog KIM , Kuoyuan HSU , Jacklyn CHANG
CPC分类号： G06F17/5072 , G11C15/04 , H03K19/20
摘要： A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates.
摘要翻译： 存储器包括多个可内容寻址存储器（CAM）单元和与多个CAM单元相关联的汇总电路。 汇总电路包括第一级逻辑门和第二级逻辑门。 第一级逻辑门具有各自被配置为接收多个CAM单元中对应的一个的单元的输出的输入。 逻辑门的第二级具有各自被配置为接收第一级逻辑门的对应的一个的输出的输入。
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公开(公告)号：US20140250416A1
公开(公告)日：2014-09-04
申请号：US14279406
申请日：2014-05-16
申请人： Young Seog KIM , Kuoyuan HSU , Jacklyn CHANG
发明人： Young Seog KIM , Kuoyuan HSU , Jacklyn CHANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G11C15/04 , H03K19/20
摘要： A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot.
摘要翻译： 设计内容寻址存储器（CAM）的方法包括将CAM单元与汇总电路相关联。 汇总电路包括第一级逻辑门和第二级逻辑门。 第一级逻辑门具有各自被配置为接收多个CAM单元中对应的一个的单元的输出的输入。 逻辑门的第二级具有各自被配置为接收第一级逻辑门的对应的一个的输出的输入。 选择第一级逻辑门或第二级逻辑门中的至少一个的逻辑门具有奇数个输入引脚，使得输入引脚和输出引脚共享布局子时隙。
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公开(公告)号：US20100328982A1
公开(公告)日：2010-12-30
申请号：US12788924
申请日：2010-05-27
申请人： Young Seog KIM , Kuoyuan HSU , Jacklyn CHANG
发明人： Young Seog KIM , Kuoyuan HSU , Jacklyn CHANG
CPC分类号： G06F17/5072 , G11C15/04 , H03K19/20
摘要： A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries.
摘要翻译： 静态CAM包括多个条目E，每个条目E包括多个CAM单元B和概要S.每个CAM单元B与存储单元M和比较器C相关联。通常，CAM接收到i个查找数据 线条。 当接收到数据时，存储器单元M提供CAM单元B中对应的比较器C的比较数据，以将比较的数据与接收到的数据进行比较。 如果所有比较的数据匹配所有接收到的数据行的条目，则该条目的命中。 但是，如果任何比较的数据与相应的数据行不匹配，那么该行有一个缺失，因此该条目的缺失。 根据应用程序，如果有一个或多个条目的命中，CAM将返回一个地址。
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公开(公告)号：US20110280096A1
公开(公告)日：2011-11-17
申请号：US13025668
申请日：2011-02-11
申请人： Annie LUM , Derek C. TAO , Young Seog KIM
发明人： Annie LUM , Derek C. TAO , Young Seog KIM
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.
摘要翻译： 存储电路包括以列方式设置的第一多个存储器阵列。 存储器电路包括第一多个保持器，每个保持器与第一多个存储器阵列中的对应的一个存储器阵列电耦合。 第一限流器与第一多个保持器电耦合并共享。 第一多个扇区开关各自在第一限流器和第一多个保持器中的相应一个之间电耦合。
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公开(公告)号：US20120182819A1
公开(公告)日：2012-07-19
申请号：US13429082
申请日：2012-03-23
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译： 电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管，耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管，其具有耦合到第二节点的源极，耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。 第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。 第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。 当第一PMOS晶体管，控制晶体管和第一NMOS晶体管导通时，第一节点电压降低，而第二电压升高。
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公开(公告)号：US20120134220A1
公开(公告)日：2012-05-31
申请号：US13111231
申请日：2011-05-19
申请人： Young Seog KIM , Young Suk KIM
发明人： Young Seog KIM , Young Suk KIM
CPC分类号： G11C11/419 , G11C8/08
摘要： A circuit includes a word line driver for driving a world line and a tracking word line driver for driving a tracking word line. The pulse width of a world line signal on the world line is driven to be larger than that of a tracking world line signal on the tracking world line to assist writing under difficult conditions. Because the tracking word line signal is activated later than the word line signal being activated but is deactivated at the same time with the word line, the pulse width of the word line signal is larger.
摘要翻译： 电路包括用于驱动世界线的字线驱动器和用于驱动跟踪字线的跟踪字线驱动器。 世界线上的世界线信号的脉冲宽度被驱动为大于跟踪世界线上的跟踪世界线信号的脉冲宽度，以帮助在困难条件下进行写入。 由于跟踪字线信号比字线信号被激活的时间晚，而且与字线同时被去激活，所以字线信号的脉冲宽度较大。
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公开(公告)号：US20120019312A1
公开(公告)日：2012-01-26
申请号：US12843366
申请日：2010-07-26
IPC分类号： G05F3/02
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
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公开(公告)号：US20120014201A1
公开(公告)日：2012-01-19
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
发明人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译： 一种存储器，包括：布置成多行和多列的多个存储单元。 所述多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点，电耦合在一起并被配置为接收第一电压或 该列中的多个存储单元的第二电压和多个内部接地节点。 内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。
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公开(公告)号：US20130215693A1
公开(公告)日：2013-08-22
申请号：US13399877
申请日：2012-02-17
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C7/222 , G11C11/41 , G11C29/50012 , G11C2029/5002
摘要： A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
摘要翻译： 确定时间延迟以覆盖具有跟踪电路的存储器宏中的存储器单元的定时。 基于时间延迟，确定与时间延迟相对应的电容。 使用具有确定的电容的电容器。 电容器耦合到跟踪电路的跟踪单元的第一数据线。 第一数据线的第一转变导致存储器单元的第二数据线的第一转变。
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公开(公告)号：US20120008376A1
公开(公告)日：2012-01-12
申请号：US12832320
申请日：2010-07-08
申请人： Kuoyuan (Peter) HSU , Yukit TANG , Derek TAO , Young Seog KIM
发明人： Kuoyuan (Peter) HSU , Yukit TANG , Derek TAO , Young Seog KIM
CPC分类号： G11C11/419 , G11C7/00 , G11C11/413 , H01L27/11
摘要： Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.
摘要翻译： 一些实施例涉及一种存储器阵列，包括：布置成多行和多列的多个存储单元; 其中所述多列的列包括列接地节点; 至少两个电压源被配置为选择性地耦合到所述列接地节点; 以及多个存储单元，其具有多个内部接地节点，所述多个内部接地节点电耦合在一起并连接到所述列接地节点。
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