-
公开(公告)号：US20120061840A1
公开(公告)日：2012-03-15
申请号：US13298312
申请日：2011-11-17
IPC分类号： H01L23/532
CPC分类号： H01L21/76811
摘要： A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer.
摘要翻译： 公开了一种双镶嵌结构。 双镶嵌结构包括：基底，其上包括镶嵌在基底介电层中的基底电介质层和下部布线层; 基底上的电介质层; 在所述电介质层中的通孔开口，其中所述通孔开口与所述下布线层不对准，从而暴露所述下布线层的一部分和所述基底电介质层的一部分，其中所述通孔开口包括具有凹陷区域的底部; 通过所述通孔开口的内表面的阻挡层，并且覆盖所述露出的下布线层和所述基底介电层，其中仅所述阻挡层填充所述凹陷区域; 以及填充阻挡层上的通孔开口的铜层。
-
公开(公告)号：US07977244B2
公开(公告)日：2011-07-12
申请号：US11611890
申请日：2006-12-18
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/76811 , H01L21/76814 , Y10S438/906 , Y10S438/963
摘要： Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
摘要翻译： 公开了一种半导体制造方法，其中使用含氟自由基的等离子体来蚀刻硬掩模和其下面的层; 并且使用与氟自由基反应的气体与残留的氟自由基反应来进行处理以形成含氟化合物并除去。 因此，可以避免通过存在于硬掩模中的氟自由基和钛成分的反应形成的沉淀物引起工艺缺陷。
-
公开(公告)号：US07767578B2
公开(公告)日：2010-08-03
申请号：US11621996
申请日：2007-01-11
IPC分类号： H01L21/4763
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。
-
公开(公告)号：US20080171433A1
公开(公告)日：2008-07-17
申请号：US11621996
申请日：2007-01-11
IPC分类号： H01L21/768
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF 4 N 3 N 3等离子体从双镶嵌开口选择性地去除暴露的盖层。
-
公开(公告)号：US08080877B2
公开(公告)日：2011-12-20
申请号：US12821136
申请日：2010-06-23
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。
-
公开(公告)号：US20100258941A1
公开(公告)日：2010-10-14
申请号：US12821136
申请日：2010-06-23
IPC分类号： H01L23/532
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。
-
公开(公告)号：US20080146036A1
公开(公告)日：2008-06-19
申请号：US11611890
申请日：2006-12-18
IPC分类号： H01L21/3065
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/76811 , H01L21/76814 , Y10S438/906 , Y10S438/963
摘要： Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
摘要翻译： 公开了一种半导体制造方法，其中使用含氟自由基的等离子体来蚀刻硬掩模和其下面的层; 并且使用与氟自由基反应的气体与残留的氟自由基反应来进行处理以形成含氟化合物并将其除去。 因此，可以避免通过存在于硬掩模中的氟自由基和钛成分的反应形成的沉淀物引起工艺缺陷。
-
8.发明授权Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content 有权使用具有降低的碳含量的基于硅氧烷的氧化硅盖层的双重马氏体过程公开(公告)号：US07378343B2
公开(公告)日：2008-05-27
申请号：US11164285
申请日：2005-11-17
申请人： Jei-Ming Chen , Miao-Chun Lin , Kuo-Chih Lai , Mei-Ling Chen , Cheng-Ming Weng , Chun-Jen Huang , Yu-Tsung Lai
发明人： Jei-Ming Chen , Miao-Chun Lin , Kuo-Chih Lai , Mei-Ling Chen , Cheng-Ming Weng , Chun-Jen Huang , Yu-Tsung Lai
IPC分类号： H01L21/4763
CPC分类号： H01L21/7681 , H01L21/76829
摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.
摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。
-
9.发明申请DUAL DAMASCENE PROCESS UTILIZING TEOS-BASED SILICON OXIDE CAP LAYER HAVING REDUCED CARBON CONTENT 有权使用具有减少碳含量的基于TEOS的氧化硅膜层的双重增塑工艺公开(公告)号：US20070111514A1
公开(公告)日：2007-05-17
申请号：US11164285
申请日：2005-11-17
申请人： Jei-Ming Chen , Miao-Chun Lin , Kuo-Chih Lai , Mei-Ling Chen , Cheng-Ming Weng , Chun-Jen Huang , Yu-Tsung Lai
发明人： Jei-Ming Chen , Miao-Chun Lin , Kuo-Chih Lai , Mei-Ling Chen , Cheng-Ming Weng , Chun-Jen Huang , Yu-Tsung Lai
IPC分类号： H01L21/473
CPC分类号： H01L21/7681 , H01L21/76829
摘要： A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.
摘要翻译： 双镶嵌工艺首先提供一种其上具有基底层的基底，嵌入底层的下部铜布线和覆盖嵌入的下部铜布线的下部盖层。 介电层沉积在下盖层上。 在电介质层上沉积TEOS基氧化物覆盖层。 TEOS基氧化物覆盖层的碳含量低于1×10 19原子/ cm 3。 金属硬掩模沉积在TEOS基氧化物覆盖层上。 将沟槽凹槽蚀刻到金属硬掩模和TEOS基氧化物盖层中。 然后将部分通孔特征通过沟槽凹槽蚀刻到TEOS基氧化物覆盖层和电介质层中。 沟槽凹槽和部分通孔特征被蚀刻转移到下面的电介质层中，从而形成一个双镶嵌开口，暴露下部铜布线的一部分。
-
公开(公告)号：US20130285737A1
公开(公告)日：2013-10-31
申请号：US13460112
申请日：2012-04-30
申请人： Yung Feng Lin , Chun-Jen Huang , Tzeng-Huei Shiau , Chun-Hsiung Hung , Caiyun Wu , Qifang Wang
发明人： Yung Feng Lin , Chun-Jen Huang , Tzeng-Huei Shiau , Chun-Hsiung Hung , Caiyun Wu , Qifang Wang
IPC分类号： G05F3/02
CPC分类号： H02M3/07
摘要： In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.
摘要翻译： 在一个方面，第一电荷泵具有串联布置的电荷泵级。 相邻级之间的阶段节点由第二电荷泵泵送。 在另一方面，电荷泵级的定时由命令时钟信号控制。 命令时钟信号和命令数据在与电荷泵的集成电路和外部电路之间传送。
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.022 秒)
