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公开(公告)号：US20080171433A1
公开(公告)日：2008-07-17
申请号：US11621996
申请日：2007-01-11
IPC分类号： H01L21/768
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF 4 N 3 N 3等离子体从双镶嵌开口选择性地去除暴露的盖层。
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公开(公告)号：US20120061840A1
公开(公告)日：2012-03-15
申请号：US13298312
申请日：2011-11-17
IPC分类号： H01L23/532
CPC分类号： H01L21/76811
摘要： A dual damascene structure is disclosed. The dual damascene structure includes: a substrate comprising thereon a base dielectric layer and a lower wiring layer inlaid in the base dielectric layer; a dielectric layer on the substrate; a via opening in the dielectric layer, wherein the via opening misaligns with the lower wiring layer thus exposing a portion of the lower wiring layer and a portion of the base dielectric layer, wherein the via opening comprises a bottom including a recessed area; a barrier layer lining interior surface of the via opening and covers the exposed lower wiring layer and the base dielectric layer, wherein only the barrier layer fills the recessed area; and a copper layer filling the via opening on the barrier layer.
摘要翻译： 公开了一种双镶嵌结构。 双镶嵌结构包括：基底，其上包括镶嵌在基底介电层中的基底电介质层和下部布线层; 基底上的电介质层; 在所述电介质层中的通孔开口，其中所述通孔开口与所述下布线层不对准，从而暴露所述下布线层的一部分和所述基底电介质层的一部分，其中所述通孔开口包括具有凹陷区域的底部; 通过所述通孔开口的内表面的阻挡层，并且覆盖所述露出的下布线层和所述基底介电层，其中仅所述阻挡层填充所述凹陷区域; 以及填充阻挡层上的通孔开口的铜层。
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公开(公告)号：US07977244B2
公开(公告)日：2011-07-12
申请号：US11611890
申请日：2006-12-18
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/76811 , H01L21/76814 , Y10S438/906 , Y10S438/963
摘要： Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
摘要翻译： 公开了一种半导体制造方法，其中使用含氟自由基的等离子体来蚀刻硬掩模和其下面的层; 并且使用与氟自由基反应的气体与残留的氟自由基反应来进行处理以形成含氟化合物并除去。 因此，可以避免通过存在于硬掩模中的氟自由基和钛成分的反应形成的沉淀物引起工艺缺陷。
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公开(公告)号：US07767578B2
公开(公告)日：2010-08-03
申请号：US11621996
申请日：2007-01-11
IPC分类号： H01L21/4763
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。
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公开(公告)号：US20080146036A1
公开(公告)日：2008-06-19
申请号：US11611890
申请日：2006-12-18
IPC分类号： H01L21/3065
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/76811 , H01L21/76814 , Y10S438/906 , Y10S438/963
摘要： Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
摘要翻译： 公开了一种半导体制造方法，其中使用含氟自由基的等离子体来蚀刻硬掩模和其下面的层; 并且使用与氟自由基反应的气体与残留的氟自由基反应来进行处理以形成含氟化合物并将其除去。 因此，可以避免通过存在于硬掩模中的氟自由基和钛成分的反应形成的沉淀物引起工艺缺陷。
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公开(公告)号：US08080877B2
公开(公告)日：2011-12-20
申请号：US12821136
申请日：2010-06-23
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。
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公开(公告)号：US20100258941A1
公开(公告)日：2010-10-14
申请号：US12821136
申请日：2010-06-23
IPC分类号： H01L23/532
CPC分类号： H01L21/76811
摘要： A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.
摘要翻译： 公开了一种双镶嵌工艺。 提供了具有基底电介质层，嵌入基底电介质层中的下部布线层和覆盖下部布线层的盖层的基板。 介电层沉积在盖层上。 氧化硅层沉积在电介质层上。 在氧化硅层上形成金属硬掩模。 将沟槽开口蚀刻到金属硬掩模中。 部分通孔特征被蚀刻到沟槽开口内的电介质层中。 沟槽开口和部分通孔特征被蚀刻转移到电介质层中，从而形成暴露盖层的一部分的双镶嵌开口。 执行衬垫去除步骤以通过使用CF4 / NF3等离子体从双镶嵌开口选择性地去除暴露的盖层。
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公开(公告)号：US20100105205A1
公开(公告)日：2010-04-29
申请号：US12259033
申请日：2008-10-27
申请人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
发明人： Chang-Hsiao Lee , Shih-Fang Tzou , Ming-Da Hsieh , Yu-Tsung Lai , Jyh-Cherng Yau , Jiunn-Hsiung Liao
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/3281 , H01L21/02063 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water.
摘要翻译： 提供半导体工艺。 首先，在基板上依次形成金属层，电介质层和图案化的硬掩模层。 此后，去除介电层的一部分以形成露出金属层的开口。 之后，使用清洁溶液清洁开口。 清洗液含有含量为0.00275〜3重量％的三唑化合物，含量为1〜10重量％的硫酸，含量为1〜200ppm的氢氟酸和水。
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公开(公告)号：US20090142931A1
公开(公告)日：2009-06-04
申请号：US11946875
申请日：2007-11-29
申请人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： H01L21/461 , C23F1/12
CPC分类号： H01L21/02063 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.
摘要翻译： 提供了开口蚀刻后的清洁方法。 首先，提供具有电介质层的半导体基板。 硬掩模层至少包括金属层。 然后进行开口蚀刻以形成电介质层中的至少一个开口。 进行氮（N2）处理工艺以清洁残留在开口中的具有碳 - 氟（C-F）键的聚合物残基。 最后，进行湿式清洗处理。
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公开(公告)号：US08282842B2
公开(公告)日：2012-10-09
申请号：US11946875
申请日：2007-11-29
申请人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
发明人： Chieh-Ju Wang , Jyh-Cherng Yau , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC分类号： H01B13/00
CPC分类号： H01L21/02063 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： A cleaning method following an opening etching is provided. First, a semiconductor substrate having a dielectric layer is provided. The hard mask layer includes at least a metal layer. The opening etch is then carried out to form at least an opening in the dielectric layer. A nitrogen (N2) treatment process is performed to clean polymer residues having carbon-fluorine (C—F) bonds remained in the opening. Finally, a wet cleaning process is performed.
摘要翻译： 提供了开口蚀刻后的清洁方法。 首先，提供具有电介质层的半导体基板。 硬掩模层至少包括金属层。 然后进行开口蚀刻以形成电介质层中的至少一个开口。 进行氮（N2）处理工艺以清洁残留在开口中的具有碳 - 氟（C-F）键的聚合物残基。 最后，进行湿式清洗处理。
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