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11 条记录 (耗时 0.021 秒)

    Power supply controller with multiple setting segments
    5.
    发明申请
    Power supply controller with multiple setting segments 审中-公开
    电源控制器具有多个设置段

    公开(公告)号：US20080209241A1

    公开(公告)日：2008-08-28

    申请号：US11709887

    申请日：2007-02-23

    申请人： Jim Huang

    发明人： Jim Huang

    IPC分类号： G06F1/28 ,  G06F1/32

    CPC分类号： G06F1/266 ,  G06F2200/261

    摘要： The present invention relates to a power supply controller with multiple setting segments, which comprises a display, a plurality of setting buttons, a standby indicator light and a PC connection terminal and is provided for allowing a user to easily conduct power supply control with respect to the multiple setting segments of the multiple outlets thereof by operating the setting buttons thereon directly or setting programs remotely with a computer.

    摘要翻译： 本发明涉及具有多个设置段的电源控制器，其包括显示器，多个设置按钮，备用指示灯和PC连接端子，并且被提供用于允许用户相对于 通过直接操作其上的设置按钮或者利用计算机远程设置程序，来设置多个出口的多个设置段。

    Connection device between toilet and drainpipe
    6.
    发明授权
    Connection device between toilet and drainpipe 有权
    马桶和排水管之间的连接装置

    公开(公告)号：US08607368B2

    公开(公告)日：2013-12-17

    申请号：US12427081

    申请日：2009-04-21

    申请人： Jim Huang ,  Jarl Jiang ,  Daniel Xia ,  Daniel Owen Karraker

    发明人： Jim Huang ,  Jarl Jiang ,  Daniel Xia ,  Daniel Owen Karraker

    IPC分类号： E03D11/00 ,  F16L11/12

    CPC分类号： E03D11/16

    摘要： This is a type of connection device between a toilet and a drainpipe, including a trap with an inlet connected to a toilet flush port and an outlet connected to the drainpipe. The trap has a bend part and a horizontal lower pipe connected to it. Upper and lower inner pipe walls of the horizontal lower pipe have different declination angles. There is a containing part in the inlet; and in the containing part there is a sealing part forming a sealing structure between the flush port and the inlet. This simplifies the complex structure of existing toilet drainage parts for on-site installation and for reliable use. The separated trap design includes structure that can generate a siphon phenomenon. At the time of sale, wash-down drainage can be easily transformed to siphon wash-down drainage just by changing parts, such as the trap of the toilet, thus improving the drainage effect.

    摘要翻译： 这是一种在马桶和排水管之间的连接装置，包括具有连接到马桶冲洗口的入口的陷阱和连接到排水管的出口。 陷阱具有连接到其的弯曲部分和水平下部管道。 水平下管的上，下内管壁具有不同的倾角。 进口有一个容纳部分; 并且在容纳部中存在在冲洗口和入口之间形成密封结构的密封部。 这简化了用于现场安装和可靠使用的现有厕所排水部件的复杂结构。 分离的陷阱设计包括可以产生虹吸现象的结构。 在销售时，可以通过更换部件（如马桶的陷阱）轻易地将冲洗排水改为虹吸冲洗排水，从而改善排水效果。

    Resolving pattern-loading issues of SiGe stressor
    7.
    发明授权
    Resolving pattern-loading issues of SiGe stressor 有权
    解决SiGe应激源的模式加载问题

    公开(公告)号：US07579248B2

    公开(公告)日：2009-08-25

    申请号：US11352588

    申请日：2006-02-13

    申请人： Yu-Lien Huang ,  Jim Huang ,  Ling-Yen Yeh ,  Hun-Jan Tao

    发明人： Yu-Lien Huang ,  Jim Huang ,  Ling-Yen Yeh ,  Hun-Jan Tao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielectric, forming a recess in the semiconductor adjacent the spacer, and depositing SiGe in the recess to form a SiGe stressor. The method further includes etching the SiGe stressor to improve the uniformity of SiGe stressors.

    摘要翻译： 提供了一种改善MOS器件的应力源均匀性的方法。 该方法包括在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在栅电极和栅极电介质的相应侧壁上形成间隔物，在邻近间隔物的半导体中形成凹陷，并将SiGe沉积在 凹陷形成SiGe应激源。 该方法还包括蚀刻SiGe应力器以改善SiGe应力的均匀性。

    Coupler having a solid locking pin device
    8.
    发明授权
    Coupler having a solid locking pin device 失效
    连接器具有牢固的锁定销装置

    公开(公告)号：US06685378B2

    公开(公告)日：2004-02-03

    申请号：US10124703

    申请日：2002-04-12

    申请人： Vincent Huang ,  Jim Huang

    发明人： Vincent Huang ,  Jim Huang

    IPC分类号： B23P1100

    CPC分类号： F16C11/045 ,  F16B19/06 ,  F16B21/186 ,  Y10T29/49845 ,  Y10T403/1616 ,  Y10T403/32861 ,  Y10T403/32885 ,  Y10T403/32901

    摘要： A coupler includes one or more pairs of ears each having an orifice, a lever having one end engaged between the ears and having an aperture aligned with the orifices of the ears for receiving a locking pin. The locking pin includes a head formed on one end and having an inner flat peripheral surface for solidly engaging with the ears, and includes an opening formed in a peripheral wall which may be expanded radially outward to engage with the ears, for solidly securing the locking pin to the ears. A retaining ring may solidly secure the locking pin to the ears.

    摘要翻译： 耦合器包括一对或多对耳朵，每个耳朵均具有孔口，杠杆具有接合在耳朵之间的一端，并且具有与耳朵的孔对准的孔，用于接收锁定销。 锁定销包括形成在一端并具有用于与耳朵牢固接合的内部扁平外围表面的头部，并且包括形成在周壁中的开口，该开口可以径向向外扩张以与耳朵接合，以牢固地固定锁定 针到耳朵。 固定环可以将锁定销固定到耳朵上。

    Resolving pattern-loading issues of SiGe stressor
    9.
    发明申请
    Resolving pattern-loading issues of SiGe stressor 有权
    解决SiGe应激源的模式加载问题

    公开(公告)号：US20070190730A1

    公开(公告)日：2007-08-16

    申请号：US11352588

    申请日：2006-02-13

    申请人： Yu-Lien Huang ,  Jim Huang ,  Ling-Yen Yeh ,  Hun-Jan Tao

    发明人： Yu-Lien Huang ,  Jim Huang ,  Ling-Yen Yeh ,  Hun-Jan Tao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method for improving uniformity of stressors of MOS devices is provided. The method includes forming a gate dielectric over a semiconductor substrate, forming a gate electrode on the gate dielectric, forming a spacer on respective sidewalls of the gate electrode and the gate dielectric, forming a recess in the semiconductor adjacent the spacer, and depositing SiGe in the recess to form a SiGe stressor. The method further includes etching the SiGe stressor to improve the uniformity of SiGe stressors.

    摘要翻译： 提供了一种改善MOS器件的应力源均匀性的方法。 该方法包括在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在栅电极和栅极电介质的相应侧壁上形成间隔物，在邻近间隔物的半导体中形成凹陷，并将SiGe沉积在 凹陷形成SiGe应激源。 该方法还包括蚀刻SiGe应力器以改善SiGe应力的均匀性。

    Semiconductor devices and methods of manufacture thereof
    10.
    发明申请
    Semiconductor devices and methods of manufacture thereof 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20070013070A1

    公开(公告)日：2007-01-18

    申请号：US11159709

    申请日：2005-06-23

    申请人： Mong Liang ,  Hun-Jan Tao ,  Jim Huang ,  Ling-Yen Yeh ,  Yu-Lien Huang

    发明人： Mong Liang ,  Hun-Jan Tao ,  Jim Huang ,  Ling-Yen Yeh ,  Yu-Lien Huang

    IPC分类号： H01L23/52

    CPC分类号： H01L21/02123 ,  H01L21/3185 ,  H01L27/10894 ,  H01L27/11

    摘要： Novel etch stop layers for semiconductor devices and methods of forming thereof are disclosed. In one embodiment, an etch stop layer comprises tensile or compressive stress. In another embodiments, etch stop layers are formed having a first thickness in a first region of a workpiece and at least one second thickness in a second region of a workpiece, wherein the at least one second thickness is different than the first thickness. The etch stop layer may be thicker over top surfaces than over sidewall surfaces. The etch stop layer may be thicker over widely-spaced feature regions and thinner over closely-spaced feature regions.

    摘要翻译： 公开了用于半导体器件的新型蚀刻停止层及其形成方法。 在一个实施例中，蚀刻停止层包括拉伸或压缩应力。 在另一个实施例中，在工件的第一区域中形成具有第一厚度并且在工件的第二区域中具有至少一个第二厚度的蚀刻停止层，其中至少一个第二厚度不同于第一厚度。 蚀刻停止层可以在顶表面上比在侧壁表面上更厚。 蚀刻停止层可以在宽间隔的特征区域上更厚，并且在紧密间隔的特征区域上更薄。