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    Glucagon antagonists
    4.
    发明授权
    Glucagon antagonists 有权
    胰高血糖素拮抗剂

    公开(公告)号：US08981047B2

    公开(公告)日：2015-03-17

    申请号：US12739342

    申请日：2008-10-23

    申请人： Richard D. Dimarchi ,  Bin Yang

    发明人： Richard D. Dimarchi ,  Bin Yang

    IPC分类号： A61K38/26 ,  C07K14/605 ,  C07K14/00 ,  A61K38/00

    CPC分类号： C07K14/605 ,  A61K38/00

    摘要： Glucagon antagonists are provided which comprise amino acid substitutions and/or chemical modifications to glucagon sequence. In one embodiment, the glucagon antagonists comprise a native glucagon peptide that has been modified by the deletion of the first two to five amino acid residues from the N-terminus and (i) an amino acid substitution at position 9 (according to the numbering of native glucagon) or (ii) substitution of the Phe at position 6 (according to the numbering of native glucagon) with phenyl lactic acid (PLA). In another embodiment, the glucagon antagonists comprise the structure A-B-C as described herein, wherein A is PLA, an oxy derivative thereof, or a peptide of 2-6 amino acids in which two consecutive amino acids of the peptide are linked via an ester or ether bond.

    摘要翻译： 提供了包含对胰高血糖素序列的氨基酸取代和/或化学修饰的胰高血糖素拮抗剂。 在一个实施方案中，胰高血糖素拮抗剂包含通过从N-末端缺失前两个至五个氨基酸残基而修饰的天然胰高血糖素肽，以及（i）在第9位的氨基酸取代（根据 天然胰高血糖素）或（ii）用苯基乳酸（PLA）取代第6位的Phe（根据天然胰高血糖素的编号）。 在另一个实施方案中，胰高血糖素拮抗剂包含如本文所述的结构ABC，其中A是PLA，其氧衍生物或2-6个氨基酸的肽，其中肽的两个连续氨基酸经由酯或醚连接 键。

    Use of band edge gate metals as source drain contacts
    6.
    发明授权
    Use of band edge gate metals as source drain contacts 有权
    使用带边栅极金属作为源极漏极触点

    公开(公告)号：US08741753B2

    公开(公告)日：2014-06-03

    申请号：US13611736

    申请日：2012-09-12

    申请人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    发明人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

    IPC分类号： H01L21/20 ,  H01L21/3205 ,  H01L21/00

    CPC分类号： H01L29/7833 ,  H01L21/28512 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

    摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

    摘要翻译： 一种器件包括形成在半导体衬底中的沟道上方的栅叠层。 栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。 该装置还包括邻近通道的源极和漏极接触。 源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

    MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture
    8.
    发明授权
    MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture 有权
    具有均匀薄的硅化物层的MOSFET集成电路及其制造方法

    公开(公告)号：US08652963B2

    公开(公告)日：2014-02-18

    申请号：US13237732

    申请日：2011-09-20

    申请人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

    发明人： Bin Yang ,  Christian Lavoie ,  Emre Alptekin ,  Ahmet S. Ozcan ,  Cung D. Tran ,  Mark Raymond

    IPC分类号： H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

    摘要： An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

    摘要翻译： 提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。 一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。 在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。 该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

    WATERMARKING IMAGE BLOCK DIVISION METHOD AND DEVICE FOR WESTERN LANGUAGE WATERMARKING PROCESSING
    9.
    发明申请
    WATERMARKING IMAGE BLOCK DIVISION METHOD AND DEVICE FOR WESTERN LANGUAGE WATERMARKING PROCESSING 有权
    WATERMARKING图像块分割方法和西语言水印处理装置

    公开(公告)号：US20140003649A1

    公开(公告)日：2014-01-02

    申请号：US13997258

    申请日：2011-12-23

    申请人： Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

    发明人： Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

    IPC分类号： G06T1/00

    CPC分类号： G06T1/0021 ,  G06K9/348 ,  G06K2209/01 ,  G06T2201/0051 ,  G06T2201/0062 ,  G06T2201/0083

    摘要： The application provides a method for partitioning a watermark image with western language characters, comprising: partitioning a western language characters image along rows and columns to form a plurality of character image blocks; identifying valid character image blocks from the formed character image blocks; counting sizes of the valid character image blocks to determine if the image corresponds to a document with a large font size or a document with a small font size; dividing words in the image into a plurality of groups, wherein each divided group in the document with large font size has different numbers of words from that with small font size; and dividing equally the divided word groups into multiple portions corresponding to watermark image blocks. The application further provides a device for partitioning a watermark image with western language characters. The operability of watermark embedding process can be ensured through the above technical solution.

    摘要翻译： 该应用程序提供了一种用于用西方语言字符分割水印图像的方法，包括：沿着行和列划分西方语言字符图像以形成多个字符图像块; 从形成的字符图像块中识别有效的字符图像块; 计算有效字符图像块的大小，以确定图像是否对应于具有较大字体大小的文档或具有小字体大小的文档; 将图像中的单词划分成多个组，其中具有大字体大小的文档中的每个划分组具有与具有小字体尺寸的单词不同的字数; 并将划分的字组分成相当于水印图像块的多个部分。 该应用还提供了一种用于用西语字符分割水印图像的设备。 通过上述技术方案可以确保水印嵌入过程的可操作性。

    ETSOI with reduced extension resistance
    10.
    发明授权
    ETSOI with reduced extension resistance 有权
    ETSOI具有降低的延伸电阻

    公开(公告)号：US08518758B2

    公开(公告)日：2013-08-27

    申请号：US12726889

    申请日：2010-03-18

    申请人： Bin Yang ,  Man Fai Ng

    发明人： Bin Yang ,  Man Fai Ng

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78618 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

    摘要： A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

    摘要翻译： 在诸如极薄的SOI（ETSOI）衬底的SOI衬底上形成半导体，具有增加的延伸厚度。 实施例包括在SOI衬底上具有外延形成的含硅层（例如嵌入硅锗（eSiGe））的半导体器件。 实施例包括形成SOI衬底，在SOI衬底上外延形成含硅层，并在外延形成的含硅层上形成栅电极。 在形成栅极间隔物和源极/漏极区之后，去除栅电极和下面的含硅层，并用高k金属栅极代替。 使用外延形成的含硅层由于制造工艺侵蚀而减少SOI厚度损失，从而增加延伸厚度并降低延伸电阻。