公开(公告)号：US20130168776A1

公开(公告)日：2013-07-04

申请号：US13342435

申请日：2012-01-03

申请人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

发明人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

公开(公告)号：US08803243B2

公开(公告)日：2014-08-12

申请号：US13342435

申请日：2012-01-03

申请人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

发明人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

IPC分类号： H01L21/70

CPC分类号： H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

公开(公告)号：US20130126976A1

公开(公告)日：2013-05-23

申请号：US13298783

申请日：2011-11-17

申请人： Xiaojun Yu ,  Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang

发明人： Xiaojun Yu ,  Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.

摘要翻译： 互补金属氧化物半导体（CMOS）器件，其可以包括具有通过隔离区彼此分离的第一有源区和第二有源区的衬底。 在第一有源区上存在n型半导体器件，其包括具有第一栅极介电层和n型功函数金属层的第一栅极结构，其中n型功函数层不延伸到隔离区 。 p型半导体器件存在于第二有源区，其包括具有第二栅极介电层和p型功函数金属层的第二栅极结构，其中p型功函数层不延伸到隔离区 。 连接栅极结构跨越隔离区域延伸成与第一栅极结构和第二栅极结构直接接触。

公开(公告)号：US08476706B1

公开(公告)日：2013-07-02

申请号：US13343472

申请日：2012-01-04

申请人： Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

发明人： Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651

摘要： A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

摘要翻译： 通过在硅表面上沉积硅碳合金层，在硅表面上提供硅的δ掺杂，硅表面可以是体硅衬底的水平表面，绝缘体上半导体衬底的顶部硅层的水平表面， 或硅片的垂直表面。 可以通过在PFET区域中而不是在NFET区域中选择性地沉积硅锗合金层来区分p型场效应晶体管（PFET）区域和n型场效应晶体管（NFET）区域。 PFET区域中的硅锗合金层可以覆盖或叠加在硅碳合金层上。 普通材料堆叠可用于PFET和NFET的栅极电介质和栅电极。 PFET和NFET的每个沟道包括硅碳合金层，并且通过硅锗层的存在或不存在来区分。

公开(公告)号：US20130168695A1

公开(公告)日：2013-07-04

申请号：US13343472

申请日：2012-01-04

申请人： Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

发明人： Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC分类号： H01L27/092 ,  H01L29/12 ,  H01L21/8238

CPC分类号： H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651

摘要： A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.

摘要翻译： 通过在硅表面上沉积硅碳合金层，在硅表面上提供硅的δ掺杂，硅表面可以是体硅衬底的水平表面，绝缘体上半导体衬底的顶部硅层的水平表面， 或硅片的垂直表面。 可以通过在PFET区域中而不是在NFET区域中选择性地沉积硅锗合金层来区分p型场效应晶体管（PFET）区域和n型场效应晶体管（NFET）区域。 PFET区域中的硅锗合金层可以覆盖或叠加在硅碳合金层上。 普通材料堆叠可用于PFET和NFET的栅极电介质和栅电极。 PFET和NFET的每个沟道包括硅碳合金层，并且通过硅锗层的存在或不存在来区分。

公开(公告)号：US08466496B2

公开(公告)日：2013-06-18

申请号：US13298783

申请日：2011-11-17

申请人： Xiaojun Yu ,  Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang

发明人： Xiaojun Yu ,  Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823871 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.

摘要翻译： 互补金属氧化物半导体（CMOS）器件，其可以包括具有通过隔离区彼此分离的第一有源区和第二有源区的衬底。 在第一有源区上存在n型半导体器件，其包括具有第一栅极介电层和n型功函数金属层的第一栅极结构，其中n型功函数层不延伸到隔离区 。 p型半导体器件存在于第二有源区，其包括具有第二栅极介电层和p型功函数金属层的第二栅极结构，其中p型功函数层不延伸到隔离区 。 连接栅极结构跨越隔离区域延伸成与第一栅极结构和第二栅极结构直接接触。

公开(公告)号：US20120108017A1

公开(公告)日：2012-05-03

申请号：US13347014

申请日：2012-01-10

申请人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

发明人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC分类号： H01L21/782 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

摘要翻译： 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US08354309B2

公开(公告)日：2013-01-15

申请号：US13347014

申请日：2012-01-10

申请人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

发明人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

摘要翻译： 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US08106455B2

公开(公告)日：2012-01-31

申请号：US12432927

申请日：2009-04-30

申请人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

发明人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

摘要翻译： 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US20100276753A1

公开(公告)日：2010-11-04

申请号：US12432927

申请日：2009-04-30

申请人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

发明人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8236

CPC分类号： H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

摘要翻译： 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。