公开(公告)号：US06809569B2

公开(公告)日：2004-10-26

申请号：US10085782

申请日：2002-02-28

Applicant: Yueyong Wang ,  Chanh Tran

Inventor： Yueyong Wang ,  Chanh Tran

IPC: H03K3017

CPC classification number: G05F3/262

Abstract: A circuit includes a first node having a first variable voltage and a second node having a second variable voltage. A clock signal generates the first variable and second variable voltages. A first transistor is coupled to the first node and provides a first current responsive to a first control voltage being applied to the first transistor gate. A second transistor is coupled to the second node and provides a second current responsive to a second control voltage being applied to the second transistor gate. A first control circuit is coupled to the first transistor gate and the second node. The first control circuit provides the first control voltage responsive to the first variable voltage. A second control circuit is coupled to the second transistor gate and the first node. The second control circuit provides the second control voltage responsive to the second variable voltage. The first and second currents are used to provide a duty cycle correction signal.

Abstract translation: 电路包括具有第一可变电压的第一节点和具有第二可变电压的第二节点。 时钟信号产生第一可变电压和第二可变电压。 第一晶体管耦合到第一节点并提供响应于施加到第一晶体管栅极的第一控制电压的第一电流。 第二晶体管耦合到第二节点，并响应于施加到第二晶体管栅极的第二控制电压提供第二电流。 第一控制电路耦合到第一晶体管栅极和第二节点。 第一控制电路响应于第一可变电压提供第一控制电压。 第二控制电路耦合到第二晶体管栅极和第一节点。 第二控制电路响应于第二可变电压提供第二控制电压。 第一和第二电流用于提供占空比校正信号。

公开(公告)号：US06819137B1

公开(公告)日：2004-11-16

申请号：US10237963

申请日：2002-09-10

Applicant: Yueyong Wang ,  Jade Kizer ,  Chanh Tran ,  Benedict Lau

Inventor： Yueyong Wang ,  Jade Kizer ,  Chanh Tran ,  Benedict Lau

IPC: H03K19094

CPC classification number: H03K19/018528

Abstract: A technique for voltage level shifting in input circuitry is disclosed. In one exemplary embodiment, the technique may be realized as a method for voltage level shifting input signals. This method may comprise receiving first and second input signals having first and second voltage levels, respectively, and then differentially amplifying the first and second input signals so as to generate first and second amplified voltage signals having first and second amplified voltage levels, respectively, wherein the first and second amplified voltage signals are substantially complementary. This method may then comprise reducing the first and second amplified voltage levels of the first and second amplified voltage signals so as to generate first and second level shifted amplified voltage signals having first and second level shifted amplified voltage levels, respectively.

Abstract translation: 公开了一种用于输入电路中的电压电平移位的技术。 在一个示例性实施例中，该技术可以被实现为用于电压电平移位输入信号的方法。 该方法可以包括分别接收具有第一和第二电压电平的第一和第二输入信号，然后差分放大第一和第二输入信号，以分别产生具有第一和第二放大电压电平的第一和第二放大电压信号，其中 第一和第二放大电压信号是基本互补的。 该方法可以包括减小第一和第二放大电压信号的第一和第二放大电压电平，以分别产生具有第一和第二电平移位放大电压电平的第一和第二电平移位放大电压信号。

公开(公告)号：US06803823B2

公开(公告)日：2004-10-12

申请号：US10184148

申请日：2002-06-27

Applicant: Yueyong Wang ,  Chanh Tran

Inventor： Yueyong Wang ,  Chanh Tran

IPC: H03F304

CPC classification number: H03F3/45739 ,  H03F3/45188 ,  H03F2203/45642 ,  H03F2203/45686

Abstract: A circuit, apparatus and method for providing a balanced differential signal from incoming serial data having high or low voltage swings are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a voltage source and a current source coupled to a node. A first electrical path is coupled to the voltage source and the node. A second electrical path is coupled to the voltage source and the node. The first path includes a first transistor having a first gate and a first channel. The first transistor gate is adapted to receive a reference voltage. The second path includes a second transistor having a second gate and a second channel. The second transistor gate is adapted to receive a data voltage that is variable as a positive and negative voltage relative to the reference voltage. A variable resistor is coupled to the first electrical path and the second electrical path, and provides a predetermined resistance responsive to a control signal. A signal processing circuit is coupled to the variable resistor and the node. The signal processing circuit generates a control signal responsive to the node voltage.

Abstract translation: 在本发明的实施例中提供了一种用于在具有高电压或低电压摆幅的输入串行数据中提供平衡差分信号的电路，装置和方法。 在本发明的实施例中，电路包括耦合到节点的电压源和电流源。 第一电路连接到电压源和节点。 第二电路连接到电压源和节点。 第一路径包括具有第一栅极和第一沟道的第一晶体管。 第一晶体管栅极适于接收参考电压。 第二路径包括具有第二栅极和第二沟道的第二晶体管。 第二晶体管栅极适于接收相对于参考电压可变为正负电压的数据电压。 可变电阻器耦合到第一电路径和第二电路径，并且响应于控制信号提供预定电阻。 信号处理电路耦合到可变电阻器和节点。 信号处理电路响应于节点电压产生控制信号。

公开(公告)号：US20050160247A1

公开(公告)日：2005-07-21

申请号：US11078577

申请日：2005-03-11

Applicant: John Dillon ,  Nancy Dillon ,  Kevin Donnelly ,  Mark Johnson ,  Chanh Tran

Inventor： John Dillon ,  Nancy Dillon ,  Kevin Donnelly ,  Mark Johnson ,  Chanh Tran

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/405 ,  G06F13/4022 ,  G06F13/4243

Abstract: A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.

Abstract translation: 收发器设备包括发射器，用于将信号通过多个导体传输到存储器件。 接口从耦合到控制器设备的串行通信路径接收控制信息。 控制信息作为使用发射机的信号提供给存储装置。 寄存器存储控制参数，该控制参数指定使用发射机将多个导体发送到存储器件的信号的驱动强度调整。

公开(公告)号：US06643752B1

公开(公告)日：2003-11-04

申请号：US09458582

申请日：1999-12-09

Applicant: Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon

Inventor： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon

IPC: G06F1200

CPC classification number: G06F13/405 ,  G06F13/4022 ,  G06F13/4243

Abstract: A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.

Abstract translation: 描述收发器系统。 次存储器模块耦合到主信道，用于从控制器接收数据和信号。 辅助存储器模块包括用于将数据和控制信号发送到存储器的存储器和辅助通道。 次存储器模块还包括耦合到主信道和次信道的收发器。 收发器被设计为将次级通道与主通道电隔离。 收发器是一个低延迟中继器，允许来自控制器的数据和控制信号到达存储器，使得来自控制器的数据请求的等待时间与收发器与控制器的距离无关。

公开(公告)号：US20070257693A1

公开(公告)日：2007-11-08

申请号：US11417964

申请日：2006-05-03

Applicant: Bret Stott ,  Philip Yeung ,  John Brooks ,  Benedict Lau ,  Chanh Tran ,  Eugene Ho

Inventor： Bret Stott ,  Philip Yeung ,  John Brooks ,  Benedict Lau ,  Chanh Tran ,  Eugene Ho

IPC: G01R31/02

CPC classification number: G01R31/31716 ,  G11C29/022

Abstract: An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

Abstract translation: 描述了集成电路。 集成电路包括包括发射机和接收机的接口电路。 集成电路中的发生器选择性地耦合到发射机。 发生器将提供在测试操作模式期间由发射器输出的测试序列。 集成电路中的存储器选择性地耦合到发生器和接收器。 存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。 集成电路中的逻辑电路是比较测试序列和信号。

公开(公告)号：US20050057275A1

公开(公告)日：2005-03-17

申请号：US10662204

申请日：2003-09-12

Applicant: Huy Ngyuen ,  Chanh Tran

Inventor： Huy Ngyuen ,  Chanh Tran

IPC: H03K19/00 ,  H03K19/003

CPC classification number: H03K19/00384 ,  H03K19/0005

Abstract: Disclosed is an output driver having an output port for outputting a data signal, a level shifter for driving a current to the output port in response to a current control input, an adjustable impedance controller for generating an impedance adjustment signal; an output impedance compensator for adjusting the impedance of the level shifter in accordance with the impedance adjustment signal and in accordance with a reference voltage, and a tracking circuit, including a process and temperature monitor responsive to manufacturing process and temperature variations of the output driver, a frequency monitor responsive to the frequency of an input clock signal, and a voltage supply monitor responsive to an internal power supply voltage. The process and temperature monitor, frequency monitor and voltage supply monitor are interconnected so as to generate the reference voltage.

Abstract translation: 公开了一种输出驱动器，具有用于输出数据信号的输出端口，用于响应于电流控制输入将电流驱动到输出端口的电平移位器，用于产生阻抗调整信号的可调阻抗控制器; 输出阻抗补偿器，用于根据阻抗调整信号并根据参考电压调整电平移位器的阻抗;以及跟踪电路，包括响应于制造过程和输出驱动器的温度变化的过程和温度监视器， 响应于输入时钟信号的频率的频率监视器和响应于内部电源电压的电压供应监视器。 过程和温度监视器，频率监视器和电压监视器互连，以产生参考电压。

公开(公告)号：US20070118711A1

公开(公告)日：2007-05-24

申请号：US11624966

申请日：2007-01-19

Applicant: Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

Inventor： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

IPC: G06F13/00

CPC classification number: G06F13/405 ,  G06F13/4022 ,  G06F13/4243

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

公开(公告)号：US20070011426A1

公开(公告)日：2007-01-11

申请号：US11465230

申请日：2006-08-17

Applicant: Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

Inventor： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John Dillon ,  Nancy Dillon

IPC: G06F13/00

CPC classification number: G06F13/405 ,  G06F13/4022 ,  G06F13/4243

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract translation: 在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。 第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。 重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。

公开(公告)号：US08086812B2

公开(公告)日：2011-12-27

申请号：US11465230

申请日：2006-08-17

Applicant: Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon ,  Nancy D. Dillon, legal representative

Inventor： Kevin Donnelly ,  Mark Johnson ,  Chanh Tran ,  John B. Dillon

IPC: G06F12/00

CPC classification number: G06F13/405 ,  G06F13/4022 ,  G06F13/4243

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract translation: 在收发机系统中，第一接口使用第一时钟信号从第一信道接收数据，并使用第二时钟信号将数据发送到第一信道。 第二接口使用第三时钟信号从第二信道接收数据，并使用第四时钟信号将数据发送到第二信道。 重新定时器使用第一时钟信号从第一信道接收数据，并使用第四时钟信号将数据重传到第二信道。