-
公开(公告)号:US20140231827A1
公开(公告)日:2014-08-21
申请号:US14141174
申请日:2013-12-26
IPC分类号: H01L29/47 , H01L29/45 , H01L29/16 , H01L21/285 , H01L29/78
CPC分类号: H01L29/47 , H01L21/0485 , H01L21/28518 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/78 , H01L29/7806 , H01L29/7813
摘要: A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.
摘要翻译: 一种制造半导体器件的方法包括:在碳化硅层的一个主表面上的第一区域中形成欧姆电极,将欧姆电极硅化,并在第二区域中形成肖特基电极 具有自对准的碳化硅层。 在没有形成欧姆电极的情况下暴露第二区域。
-
2.
公开(公告)号:US20170012122A1
公开(公告)日:2017-01-12
申请号:US15116288
申请日:2014-10-06
申请人: Hidefumi TAKAYA , Jun SAITO , Akitaka SOENO , Kimimori HAMADA , Shoji MIZUNO , Sachiko AOI , Yukihiko WATANABE
发明人: Hidefumi TAKAYA , Jun SAITO , Akitaka SOENO , Kimimori HAMADA , Shoji MIZUNO , Sachiko AOI , Yukihiko WATANABE
IPC分类号: H01L29/78 , H01L29/16 , H01L21/761 , H01L29/06 , H01L29/66
CPC分类号: H01L29/7811 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0649 , H01L29/0661 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要: A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.
摘要翻译: 半导体器件包括围绕其中设置有多个栅极沟槽的区域的端接沟槽; 与端子沟槽的下端接触的p型下端区域; p型外周区域,其从外周侧与所述端接沟槽接触并露出在所述半导体器件的表面上; 多个p型保护环区域,设置在p型外周区域的外周侧并露出在表面上; 以及将p型外周区域与保护环区域分离并将保护环区域彼此分离的n型外周区域。
-
公开(公告)号:US20120043582A1
公开(公告)日:2012-02-23
申请号:US13210624
申请日:2011-08-16
申请人: Masaki KOYAMA , Yasushi OOKURA , Akitaka SOENO , Tatsuji NAGAOKA , Takahide SUGIYAMA , Sachiko AOI , Hiroko IGUCHI
发明人: Masaki KOYAMA , Yasushi OOKURA , Akitaka SOENO , Tatsuji NAGAOKA , Takahide SUGIYAMA , Sachiko AOI , Hiroko IGUCHI
IPC分类号: H01L29/739 , H01L21/331
CPC分类号: H01L29/8611 , H01L21/263 , H01L21/26506 , H01L21/26513 , H01L21/266 , H01L29/063 , H01L29/0834 , H01L29/32 , H01L29/7397
摘要: There is known a semiconductor device in which an IGBT structure is provided in an IGBT area and a diode structure is provided in a diode area, the IGBT area and the diode area are both located within a same substrate, and the IGBT area is adjacent to the diode area. In this type of semiconductor device, a phenomenon that carriers accumulated within the IGBT area flow into the diode area when the IGBT structure is turned off. In order to prevent this phenomenon, a region of shortening lifetime of carriers is provided at least in a sub-area that is within said IGBT area and adjacent to said diode area. In the sub-area, emitter of IGBT structure is omitted.
摘要翻译: 已知在IGBT区域中设置IGBT结构并且在二极管区域中设置二极管结构的IGBT半导体器件,IGBT面积和二极管面积都位于同一衬底内,并且IGBT区域与 二极管面积。 在这种类型的半导体器件中,当IGBT结构关断时,积聚在IGBT区域内的载流子流入二极管区域的现象。 为了防止这种现象,至少在所述IGBT区域内并与所述二极管区域相邻的子区域中提供载流子缩短寿命的区域。 在子区域中,省略了IGBT结构的发射极。
-
公开(公告)号:US20120132955A1
公开(公告)日:2012-05-31
申请号:US13366896
申请日:2012-02-06
申请人: Jun SAITO , Sachiko AOI , Takahide SUGIYAMA
发明人: Jun SAITO , Sachiko AOI , Takahide SUGIYAMA
IPC分类号: H01L29/739
CPC分类号: H01L27/0664 , H01L29/0834 , H01L29/32 , H01L29/7397 , H01L29/861
摘要: A diode region and an IGBT region are formed in a semiconductor layer of a semiconductor device. A lifetime controlled region is formed in the semiconductor layer. In a plan view, the lifetime controlled region has a first lifetime controlled region located in the diode region and a second lifetime controlled region located in a part of the IGBT region. The second lifetime controlled region extends from a boundary of the diode region and the IGBT region toward the IGBT region. In the plan view, a tip of the second lifetime controlled region is located in a forming area of the body region in the IGBT region.
摘要翻译: 二极管区域和IGBT区域形成在半导体器件的半导体层中。 在半导体层中形成寿命受控区域。 在平面图中,寿命受控区域具有位于二极管区域中的第一寿命受控区域和位于IGBT区域的一部分中的第二寿命受控区域。 第二寿命受控区域从二极管区域和IGBT区域的边界向IGBT区域延伸。 在平面图中,第二寿命受控区域的前端位于IGBT区域的体区的形成区域中。
-
公开(公告)号:US20160005844A1
公开(公告)日:2016-01-07
申请号:US14767370
申请日:2013-02-13
申请人: Keisuke KIMURA , Satoru KAMEYAMA , Masaki KOYAMA , Sachiko AOI
发明人: Keisuke KIMURA , Satoru KAMEYAMA , Masaki KOYAMA , Sachiko AOI
IPC分类号: H01L29/739 , H01L27/06 , H01L29/10
CPC分类号: H01L29/7397 , H01L27/0629 , H01L27/0664 , H01L29/0696 , H01L29/0834 , H01L29/1095
摘要: A semiconductor device in which an IGBT region and a diode region are formed on one semiconductor substrate is disclosed. The IGBT region includes: a body layer of a first conductivity type that is formed on a front surface of the semiconductor substrate; a body contact layer of the first conductivity type that is partially formed on a front surface of the body layer and has a higher impurity concentration of the first conductivity type than the body layer; an emitter layer of a second conductivity type that is partially formed on the front surface of the body layer; a drift layer; a collector layer; and a gate electrode. In the semiconductor device, a part of the body contact layer placed at a long distance from the diode region is made larger than a part of the body contact layer placed at a short distance from the diode region.
摘要翻译: 公开了在一个半导体衬底上形成IGBT区域和二极管区域的半导体器件。 IGBT区域包括:形成在半导体衬底的前表面上的第一导电类型的主体层; 所述第一导电类型的体接触层部分地形成在所述主体层的前表面上,并且具有比所述主体层更高的第一导电类型的杂质浓度; 第二导电类型的发射极层,部分地形成在所述主体层的前表面上; 漂移层 收集层; 和栅电极。 在半导体器件中,与二极管区域长距离放置的身体接触层的一部分被制成大于放置在与二极管区域相距很短距离的身体接触层的一部分。
-
-
-
-