公开(公告)号：US20170012122A1

公开(公告)日：2017-01-12

申请号：US15116288

申请日：2014-10-06

申请人： Hidefumi TAKAYA ,  Jun SAITO ,  Akitaka SOENO ,  Kimimori HAMADA ,  Shoji MIZUNO ,  Sachiko AOI ,  Yukihiko WATANABE

发明人： Hidefumi TAKAYA ,  Jun SAITO ,  Akitaka SOENO ,  Kimimori HAMADA ,  Shoji MIZUNO ,  Sachiko AOI ,  Yukihiko WATANABE

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7811 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

摘要翻译： 半导体器件包括围绕其中设置有多个栅极沟槽的区域的端接沟槽; 与端子沟槽的下端接触的p型下端区域; p型外周区域，其从外周侧与所述端接沟槽接触并露出在所述半导体器件的表面上; 多个p型保护环区域，设置在p型外周区域的外周侧并露出在表面上; 以及将p型外周区域与保护环区域分离并将保护环区域彼此分离的n型外周区域。

公开(公告)号：US20080087949A1

公开(公告)日：2008-04-17

申请号：US11854183

申请日：2007-09-12

申请人： Michiaki MARUOKA ,  Kimimori HAMADA ,  Hidefumi TAKAYA

发明人： Michiaki MARUOKA ,  Kimimori HAMADA ,  Hidefumi TAKAYA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734

摘要： A p-type epitaxial layer is formed on an n+-type substrate and then a buried n-type region is formed at a boundary between the n+-type substrate and the p-type epitaxial layer by ion implantation. Subsequently, a trench is formed so as to reach the n+-type substrate, passing through the p-type epitaxial layer and the buried n-type region. Then, a gate electrode is formed so as to deeply extend into the trench, i.e. to a position opposed to the buried n-type region. In a vertical MOSFET with this structure, when a positive voltage is applied to the gate electrode, an accumulation layer with a low resistance is formed in the buried n-type region, thereby reducing an on-resistance.

摘要翻译： 在n +型衬底上形成p型外延层，然后通过离子注入在n +型衬底和p型外延层之间的边界处形成掩埋的n型区域。 随后，形成沟槽，以便到达n +型衬底，穿过p型外延层和埋入的n型区域。 然后，形成栅电极，以便深深地延伸到沟槽中，即形成到与掩埋的n型区域相对的位置。 在具有这种结构的垂直MOSFET中，当向栅电极施加正电压时，在埋入的n型区域中形成具有低电阻的累积层，从而降低导通电阻。

公开(公告)号：US20140054688A1

公开(公告)日：2014-02-27

申请号：US14074212

申请日：2013-11-07

申请人： Hidefumi TAKAYA ,  Kimimori HAMADA ,  Yuji NISHIBE

发明人： Hidefumi TAKAYA ,  Kimimori HAMADA ,  Yuji NISHIBE

IPC分类号： H01L29/78

CPC分类号： H01L29/7815 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095

摘要： Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ∑ i = 1 n  ( R Mi × k Mi ) - ∑ i = 1 n  ( R Si × k Si ) ] / ∑ i = 1 n  ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

摘要翻译： 提供了能够降低电流感测比的温度变化并精确检测电流的半导体器件。在半导体器件中，调整每个半导体层的杂质浓度和厚度中的至少一个，使得通过a 以下等式小于预定值：[Σi = 1 n（R Mi×k Mi） - Σi = 1 n（R Si×k Si）] /Σi = 1 n（R Mi×k Mi）其中主要元素域的第i个半导体层（i = 1至n）的温度依赖性电阻变化率为RMi; 主元件区域的第i个半导体层相对于整个主要元件区域的电阻比为kMi; 感测元件畴的第i个半导体层的温度依赖性电阻变化率为RSi; 并且感测元件畴的第i个半导体层与整个感测元件畴的电阻比为kSi。

公开(公告)号：US20120007222A1

公开(公告)日：2012-01-12

申请号：US13241429

申请日：2011-09-23

申请人： Tadashi MISUMI ,  Kimimori HAMADA

发明人： Tadashi MISUMI ,  Kimimori HAMADA

IPC分类号： H01L27/08

CPC分类号： H01L29/861 ,  H01L29/36 ,  H01L29/66136 ,  H01L29/868

摘要： The present specification provides a method of efficiently manufacturing diodes in which recovery surge voltage is hardly generated.The method manufactures a diode including a high concentration n-type semiconductor layer, a medium concentration n-type semiconductor layer formed on the high concentration n-type semiconductor layer, a low concentration n-type semiconductor layer formed on the medium concentration n-type semiconductor layer, and a p-type semiconductor layer formed on the low concentration n-type semiconductor layer. This manufacturing method includes growing the low concentration n-type semiconductor layer on an n-type semiconductor substrate by epitaxial growth, wherein a concentration of n-type impurities in the low concentration n-type semiconductor layer is lower than that in the n-type semiconductor substrate, and forming the high concentration n-type semiconductor layer by injecting n-type impurities to a lower surface of the n-type semiconductor substrate.

摘要翻译： 本说明书提供了一种有效地制造难以产生回收浪涌电压的二极管的方法。 该方法制造二极管，其包括高浓度n型半导体层，形成在高浓度n型半导体层上的中等浓度n型半导体层，形成在介质浓度n型半导体层上的低浓度n型半导体层 半导体层和形成在低浓度n型半导体层上的p型半导体层。 该制造方法包括通过外延生长在n型半导体衬底上生长低浓度n型半导体层，其中低浓度n型半导体层中的n型杂质的浓度低于n型半导体层中的n型杂质浓度 并且通过向n型半导体衬底的下表面注入n型杂质形成高浓度n型半导体层。