公开(公告)号：US20170012122A1

公开(公告)日：2017-01-12

申请号：US15116288

申请日：2014-10-06

申请人： Hidefumi TAKAYA ,  Jun SAITO ,  Akitaka SOENO ,  Kimimori HAMADA ,  Shoji MIZUNO ,  Sachiko AOI ,  Yukihiko WATANABE

发明人： Hidefumi TAKAYA ,  Jun SAITO ,  Akitaka SOENO ,  Kimimori HAMADA ,  Shoji MIZUNO ,  Sachiko AOI ,  Yukihiko WATANABE

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7811 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

摘要翻译： 半导体器件包括围绕其中设置有多个栅极沟槽的区域的端接沟槽; 与端子沟槽的下端接触的p型下端区域; p型外周区域，其从外周侧与所述端接沟槽接触并露出在所述半导体器件的表面上; 多个p型保护环区域，设置在p型外周区域的外周侧并露出在表面上; 以及将p型外周区域与保护环区域分离并将保护环区域彼此分离的n型外周区域。

公开(公告)号：US20140231827A1

公开(公告)日：2014-08-21

申请号：US14141174

申请日：2013-12-26

申请人： Yukihiko WATANABE ,  Sachiko AOI ,  Masahiro SUGIMOTO ,  Akitaka SOENO ,  Shinichiro MIYAHARA

发明人： Yukihiko WATANABE ,  Sachiko AOI ,  Masahiro SUGIMOTO ,  Akitaka SOENO ,  Shinichiro MIYAHARA

IPC分类号： H01L29/47 ,  H01L29/45 ,  H01L29/16 ,  H01L21/285 ,  H01L29/78

CPC分类号： H01L29/47 ,  H01L21/0485 ,  H01L21/28518 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7813

摘要： A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.

摘要翻译： 一种制造半导体器件的方法包括：在碳化硅层的一个主表面上的第一区域中形成欧姆电极，将欧姆电极硅化，并在第二区域中形成肖特基电极 具有自对准的碳化硅层。 在没有形成欧姆电极的情况下暴露第二区域。

公开(公告)号：US20120043582A1

公开(公告)日：2012-02-23

申请号：US13210624

申请日：2011-08-16

申请人： Masaki KOYAMA ,  Yasushi OOKURA ,  Akitaka SOENO ,  Tatsuji NAGAOKA ,  Takahide SUGIYAMA ,  Sachiko AOI ,  Hiroko IGUCHI

发明人： Masaki KOYAMA ,  Yasushi OOKURA ,  Akitaka SOENO ,  Tatsuji NAGAOKA ,  Takahide SUGIYAMA ,  Sachiko AOI ,  Hiroko IGUCHI

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/8611 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/063 ,  H01L29/0834 ,  H01L29/32 ,  H01L29/7397

摘要： There is known a semiconductor device in which an IGBT structure is provided in an IGBT area and a diode structure is provided in a diode area, the IGBT area and the diode area are both located within a same substrate, and the IGBT area is adjacent to the diode area. In this type of semiconductor device, a phenomenon that carriers accumulated within the IGBT area flow into the diode area when the IGBT structure is turned off. In order to prevent this phenomenon, a region of shortening lifetime of carriers is provided at least in a sub-area that is within said IGBT area and adjacent to said diode area. In the sub-area, emitter of IGBT structure is omitted.

摘要翻译： 已知在IGBT区域中设置IGBT结构并且在二极管区域中设置二极管结构的IGBT半导体器件，IGBT面积和二极管面积都位于同一衬底内，并且IGBT区域与 二极管面积。 在这种类型的半导体器件中，当IGBT结构关断时，积聚在IGBT区域内的载流子流入二极管区域的现象。 为了防止这种现象，至少在所述IGBT区域内并与所述二极管区域相邻的子区域中提供载流子缩短寿命的区域。 在子区域中，省略了IGBT结构的发射极。

公开(公告)号：US20170084735A1

公开(公告)日：2017-03-23

申请号：US15365150

申请日：2016-11-30

申请人： Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Yuichi TAKEUCHI ,  Naohiro SUZUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/417 ,  H01L29/872 ,  H01L29/15 ,  H01L21/761

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US20130001639A1

公开(公告)日：2013-01-03

申请号：US13609868

申请日：2012-09-11

申请人： Shinya IWASAKI ,  Akitaka SOENO

发明人： Shinya IWASAKI ,  Akitaka SOENO

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L21/761 ,  H01L27/0761 ,  H01L29/0834 ,  H01L29/32 ,  H01L29/7397 ,  H01L29/861

摘要： A semiconductor device includes a semiconductor substrate in which a diode region and an IGBT region are formed, wherein a lower surface side of the semiconductor substrate comprises a low impurity region provided between a second conductivity type cathode region of the diode region and a first conductivity type collector region of the IGBT region. The low impurity region includes at least one of a first conductivity type first low impurity region which has a lower density of first conductivity type impurities than that in the collector region and a second conductivity type second low impurity region which has a lower density of second conductivity type impurities than that in the cathode region.

摘要翻译： 半导体器件包括其中形成二极管区域和IGBT区域的半导体衬底，其中半导体衬底的下表面侧包括设置在二极管区域的第二导电类型阴极区域和第二导电类型之间的低杂质区域 IGBT区域的集电极区域。 低杂质区域包括具有比集电极区域低的第一导电类型杂质的密度较低的第一导电类型的第一低杂质区域和具有较低密度的第二导电性的第二导电型第二低杂质区域中的至少一个 类型的杂质比阴极区域。

公开(公告)号：US20090278166A1

公开(公告)日：2009-11-12

申请号：US12436888

申请日：2009-05-07

申请人： Akitaka SOENO ,  Yukihiro Hisanaga

发明人： Akitaka SOENO ,  Yukihiro Hisanaga

IPC分类号： H01L29/739

CPC分类号： H01L29/7397 ,  H01L27/0664 ,  H01L29/861

摘要： A semiconductor device in which both an IGBT element region and a diode element region exist in the same semiconductor substrate includes a low lifetime region, which is formed in at least a part of a drift layer within the diode element region and shortens the lifetime of holes. A mean value of the lifetime of holes in the drift layer that includes the low lifetime region is shorter within the IGBT element region than within the diode element region.

摘要翻译： 在同一半导体衬底中存在IGBT元件区域和二极管元件区域的半导体器件包括低寿命区域，其形成在二极管元件区域内的漂移层的至少一部分中并缩短孔的寿命 。 包含低寿命区域的漂移层中的空穴的寿命的平均值在IGBT元件区域内比在二极管元件区域内更短。

公开(公告)号：US20170040448A1

公开(公告)日：2017-02-09

申请号：US15106918

申请日：2014-10-16

申请人： Akitaka SOENO ,  Yuji FUKUOKA

发明人： Akitaka SOENO ,  Yuji FUKUOKA

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/78

摘要： Described herein is a semiconductor device including a semiconductor substrate in which an element region and a termination region surrounding the element region are provided. The element region includes: a gate trench; a gate insulating film; and a gate electrode. The termination region includes: a plurality of termination trenches provided around the element region; an inner trench insulating layer located inside of each of the plurality of termination trenches; and an upper surface insulating layer located at an upper surface of the semiconductor substrate in the termination region. The upper surface insulating layer includes a first portion and a second portion having a thinner thickness than the first portion and located at a location separated from the element region than the first portion, and a gate wiring is located at an upper surface of the first portion and is not located at an upper surface of the second portion.

摘要翻译： 这里描述的是包括半导体衬底的半导体器件，其中设置元件区域和围绕元件区域的端接区域。 元件区域包括：栅极沟槽; 栅极绝缘膜; 和栅电极。 终端区域包括：设置在元件区域周围的多个终端沟槽; 位于所述多个终端沟槽的每一个内部的内部沟槽绝缘层; 以及位于终端区域中的半导体衬底的上表面处的上表面绝缘层。 所述上表面绝缘层包括第一部分和第二部分，所述第一部分和第二部分具有比所述第一部分更薄的厚度，并且位于与所述第一部分相比元件区域分离的位置处，并且栅极布线位于所述第一部分的上表面 并且不位于第二部分的上表面。

公开(公告)号：US20160351680A1

公开(公告)日：2016-12-01

申请号：US15114461

申请日：2014-10-06

申请人： Akitaka SOENO ,  Yuichi TAKEUCHI ,  Narumasa SOEJIMA

发明人： Akitaka SOENO ,  Yuichi TAKEUCHI ,  Narumasa SOEJIMA

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/739 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/66068 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

摘要： A method is provided for manufacturing an insulated gate type switching device. The method includes: implanting second conductivity type impurities into a surface of a semiconductor substrate so as to form a second region of a second conductivity type in the surface; forming a third region of the second conductivity type having a second conductivity type impurity density lower than the second region on the surface by epitaxial growth: and forming a trench gate electrode.

摘要翻译： 提供一种用于制造绝缘栅型开关装置的方法。 该方法包括：将第二导电型杂质注入到半导体衬底的表面中，以在表面上形成第二导电类型的第二区域; 通过外延生长形成具有比表面上的第二区域低的第二导电类型杂质密度的第二导电类型的第三区域;以及形成沟槽栅电极。

公开(公告)号：US20120080718A1

公开(公告)日：2012-04-05

申请号：US13315841

申请日：2011-12-09

申请人： Akitaka SOENO

发明人： Akitaka SOENO

IPC分类号： H01L29/739

CPC分类号： H01L27/0664 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/8611

摘要： The present teachings provide a semiconductor device comprising: an IGBT element region, a diode element region and a boundary region provided between the IGBT element region and the diode element region are formed in one semiconductor substrate. The boundary region comprises a second conductivity type first diffusion region, a first conductivity type second diffusion region, and a second conductivity type third diffusion region. A first drift region of the IGBT element region contiguously contacts the first diffusion region of the boundary region, and a second drift region of the diode element region contiguously contacts the first diffusion region of the boundary region. A first body region of the IGBT element region contiguously contacts the second diffusion region of the boundary region, and a second body region of the diode element region contiguously contacts the second diffusion region of the boundary region.

摘要翻译： 本发明提供一种半导体器件，包括：在一个半导体衬底中形成IGBT元件区域，二极管元件区域和设置在IGBT元件区域和二极管元件区域之间的边界区域。 边界区包括第二导电类型的第一扩散区，第一导电类型的第二扩散区和第二导电类型的第三扩散区。 IGBT元件区域的第一漂移区域与边界区域的第一扩散区域连续接触，二极管元件区域的第二漂移区域与边界区域的第一扩散区域连续地接触。 IGBT元件区域的第一体区域与边界区域的第二扩散区域连续接触，二极管元件区域的第二体区域与边界区域的第二扩散区域连续接触。

公开(公告)号：US20150041887A1

公开(公告)日：2015-02-12

申请号：US13982519

申请日：2012-11-21

申请人： Akitaka SOENO ,  Toshimasa YAMAMOTO

发明人： Akitaka SOENO ,  Toshimasa YAMAMOTO

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L21/047 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

摘要： A semiconductor device includes a first semiconductor layer surrounding a bottom of the trench gate, a second semiconductor layer disposed along one of end portions of the trench gate in a longitudinal direction of the trench gate, one of end portions of the second semiconductor layer contacting the body layer and the other of the end portions of the second semiconductor layer contacting the first semiconductor layer, and a connecting layer, one of end portions of the connecting layer being connected to the body layer and the other of the end portions of the connecting layer being connected to the first semiconductor layer, the connecting layer contacting the second semiconductor layer, and the connecting layer being separated from the one of the end portions of the trench gate in the longitudinal direction of the trench gate by the second semiconductor layer.

摘要翻译： 半导体器件包括围绕沟槽栅极的底部的第一半导体层，在沟槽栅极的纵向方向上沿沟槽栅极的一个端部设置的第二半导体层，第二半导体层的端部中的一个与 本体层和与第一半导体层接触的第二半导体层的另一端部和连接层，连接层的端部中的一个连接到主体层，连接层的另一个端部 连接到第一半导体层，连接层与第二半导体层接触，并且连接层通过第二半导体层在沟槽栅极的纵向方向上与沟槽栅极的一个端部分离。