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    Semiconductor device having semiconductor substrate including diode region and IGBT region
    3.
    发明授权
    Semiconductor device having semiconductor substrate including diode region and IGBT region 有权
    具有半导体衬底的半导体器件包括二极管区和IGBT区

    公开(公告)号：US08299496B2

    公开(公告)日：2012-10-30

    申请号：US13242960

    申请日：2011-09-23

    申请人： Tatsuji Nagaoka ,  Akitaka Soeno

    发明人： Tatsuji Nagaoka ,  Akitaka Soeno

    IPC分类号： H01L29/74 ,  H01L31/111

    CPC分类号： H01L21/761 ,  H01L27/0727 ,  H01L29/32 ,  H01L29/7397 ,  H01L29/861

    摘要： Provided is a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed. A separation region formed of a p-type semiconductor is formed in a range between the diode region and the IGBT region and extending from an upper surface of the semiconductor substrate to a position deeper than both a lower end of an anode region and a lower end of a body region. A diode lifetime control region is formed within a diode drift region. A carrier lifetime in the diode lifetime control region is shorter than that in the diode drift region outside the diode lifetime control region. An end of the diode lifetime control region on an IGBT region side is located right below the separation region.

    摘要翻译： 提供一种半导体器件，其包括其中形成二极管区域和IGBT区域的半导体衬底。 在二极管区域和IGBT区域之间的范围内形成由p型半导体形成的分离区域，并且从半导体衬底的上表面延伸到比阳极区域和下端部的下端更深的位置 的身体区域。 二极管寿命控制区形成在二极管漂移区内。 二极管寿命控制区域中的载流子寿命短于二极管寿命控制区域外的二极管漂移区域中的载流子寿命。 IGBT区域侧的二极管寿命控制区域的一端位于分离区域正下方。

    Semiconductor apparatus and method of manufacturing the same
    4.
    发明授权
    Semiconductor apparatus and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07368799B2

    公开(公告)日：2008-05-06

    申请号：US11227958

    申请日：2005-09-15

    申请人： Tatsuji Nagaoka

    发明人： Tatsuji Nagaoka

    IPC分类号： H01L29/00

    CPC分类号： H01L29/7813 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66734 ,  H01L29/7803

    摘要： The semiconductor apparatus is disclosed that includes a partial SOI substrate including an oxide film; a lateral first MOSFET section having a planar gate structure and formed in the portion of the partial SOI substrate where there is an oxide film; a vertical second MOSFET section having a trench gate structure and formed in the portion of the partial SOI substrate where there is no oxide film, the second MOSFET section being adjacent to the first MOSFET section. The first MOSFET section includes a first p-type base region on the oxide film. The second MOSFET section includes a second n+-type drain region, a second n-type drift region on the second n+-type drain region, and a second p-type base region in the surface portion of the second n-type drift region. The height H1 of the pn-junction between the second n-type drift region and the second p-type base region from the second n+-type drain region is set to be lower than the height H2 of the boundary between the oxide film and the first p-type base region from the second n+-type drain region to make the oxide film serve as a field plate. The semiconductor apparatus including a vertical device and a lateral device configured as described above facilitates doping the second n-type drift region heavily while securing a certain breakdown voltage, reducing the ON-resistance of the second MOSFET section, and reducing the semiconductor chip size.

    摘要翻译： 公开了包括包括氧化膜的部分SOI衬底的半导体器件; 具有平面栅极结构并形成在部分SOI衬底的存在氧化物膜的部分中的横向第一MOSFET部分; 具有沟槽栅极结构并形成在部分SOI衬底的不存在氧化膜的部分中的垂直第二MOSFET部分，第二MOSFET部分与第一MOSFET部分相邻。 第一MOSFET部分包括氧化物膜上的第一p型基极区域。 第二MOSFET部分包括第二n + +型漏极区，第二n + +型漏极区上的第二n型漂移区，以及第二p + 在第二n型漂移区域的表面部分中形成基极区域。 第二n型漂移区域和第二p型基极区域之间的pn结的高度H 1从第二n + +型漏极区域设定为低于高度H 2的氧化膜和第二p型基极区域之间的边界，从而形成氧化膜作为场板。 包括如上所述构造的垂直装置和横向装置的半导体装置有助于在确保一定的击穿电压的同时重新掺杂第二n型漂移区域，从而降低第二MOSFET部分的导通电阻并减小半导体芯片尺寸。

    Method for remote control of home-located electronic devices and a management facility
    5.
    发明授权
    Method for remote control of home-located electronic devices and a management facility 有权
    遥控家用电子设备和管理设施的方法

    公开(公告)号：US06924727B2

    公开(公告)日：2005-08-02

    申请号：US10129583

    申请日：2001-09-27

    申请人： Tatsuji Nagaoka ,  Kazuo Nomura ,  Yutaka Hiruma

    发明人： Tatsuji Nagaoka ,  Kazuo Nomura ,  Yutaka Hiruma

    IPC分类号： H04L12/28 ,  G05B23/02 ,  G05B15/00

    CPC分类号： H04L12/2814 ,  H04L12/2803 ,  H04L12/2805 ,  H04L12/2809 ,  H04L12/2827

    摘要： A security system 63 and an electronic device group 62 to be stored in a home network 6 are controlled by a home server 61. A home network management facility 5 obtains status information of the electronic device group 62 from home server 61. Home network management facility 5 displays the status of electronic device group 62 on a display unit of a terminal 1 based on the received status information. Home network management facility 5 also displays a screen for prompting input of a control instruction of the home-located electronic devices that are included in the electronic device group 62. Based on control instruction received via home server 61, home network management facility 5 performs remote control of electronic device group 62.

    摘要翻译： 存储在家庭网络6中的安全系统63和电子设备组62由家用服务器61控制。 家庭网络管理设备5从家用服务器61获得电子设备组62的状态信息。 家庭网络管理设备5基于接收的状态信息在终端1的显示单元上显示电子设备组62的状态。 家庭网络管理设备5还显示用于提示输入包括在电子设备组62中的本地定位的电子设备的控制指令的屏幕。 家庭网络管理设备5基于通过家庭服务器61接收的控制指令，执行电子设备组62的远程控制。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06903418B2

    公开(公告)日：2005-06-07

    申请号：US10678941

    申请日：2003-10-03

    申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

    发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

    IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/772

    CPC分类号： H01L29/7802 ,  H01L29/0634

    摘要： A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

    摘要翻译： 半导体器件有助于在漏极漂移区周围的半导体芯片的部分中获得更高的击穿电压并且提高其雪崩耐受能力。 根据本发明的垂直MOSFET包括漏极层; 漏极层上的漏极漂移区，包括第一交替导电型层的漏极漂移区; 在漏极层和漏极漂移区域周围的击穿耐受区域（半导体芯片的外围区域），在MOSFET的导通状态基本上不提供电流路径的击穿承受区域，击穿耐受区域在断开状态 MOSFET，包括第二交替导电类型层的击穿耐受区域和栅极焊盘下方的下部区域，以及包括第三交变导电类型层的下部区域。

    Super-junction semiconductor device and method of manufacturing the same
    7.
    发明申请
    Super-junction semiconductor device and method of manufacturing the same 有权
    超结半导体器件及其制造方法

    公开(公告)号：US20050017292A1

    公开(公告)日：2005-01-27

    申请号：US10925407

    申请日：2004-08-25

    申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

    发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

    IPC分类号： H01L29/06 ,  H01L21/331 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/76

    CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

    摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

    Super-junction semiconductor device
    8.
    发明授权
    Super-junction semiconductor device 有权
    超结半导体器件

    公开(公告)号：US06696728B2

    公开(公告)日：2004-02-24

    申请号：US10099449

    申请日：2002-03-15

    申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

    发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

    IPC分类号： H01L2976

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/7395 ,  H01L29/872

    摘要： To provide a super-junction MOSFET reducing the tradeoff relation between the on-resistance and the breakdown voltage greatly and having a peripheral structure, which facilitates reducing the leakage current in the OFF-state thereof and stabilizing the breakdown voltage thereof. The vertical MOSFET according to the invention includes a drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (peripheral region) including a second alternating conductivity type layer around drain drift region, second alternating conductivity type layer being formed of layer-shaped vertically-extending n-type regions and layer-shaped vertically-extending p-type regions laminated alternately; an n-type region around second alternating conductivity type layer; and a p-type region formed in the surface portion of n-type region to reduce the leakage current in the OFF-state of the MOSFET.

    摘要翻译： 为了提供一种超级结MOSFET，大大降低了导通电阻和击穿电压之间的折衷关系，并具有外围结构，这有助于减小其截止状态下的漏电流并稳定其击穿电压。 根据本发明的垂直MOSFET包括包括第一交变导电类型层的漏极漂移区; 包括漏极漂移区周围的第二交变导电型层的击穿耐受区域（周边区域），层叠的上下方向延伸的n型区域形成的第二交替导电型层和层叠的上下方向延伸的p型区域 交替; 围绕第二交变导电类型层的n型区域; 以及形成在n型区域的表面部分中的p型区域，以减小MOSFET的截止状态下的漏电流。

    Method of forming gallium oxide film
    9.
    发明授权
    Method of forming gallium oxide film 有权

    公开(公告)号：US11515146B2

    公开(公告)日：2022-11-29

    申请号：US16697273

    申请日：2019-11-27

    申请人： Tatsuji Nagaoka ,  Hiroyuki Nishinaka ,  Masahiro Yoshimoto

    发明人： Tatsuji Nagaoka ,  Hiroyuki Nishinaka ,  Masahiro Yoshimoto

    IPC分类号： H01L21/02

    摘要： A method of forming a gallium oxide film is provided, and the method may include supplying mist of a material solution comprising gallium atoms and chlorine atoms to a surface of a substrate while heating the substrate so as to form the gallium oxide film on the surface of the substrate, in which a molar concentration of chlorine in the material solution is equal to or more than 3.0 times and equal to or less than 4.5 times a molar concentration of gallium in the material solution.