公开(公告)号：US6147918A

公开(公告)日：2000-11-14

申请号：US165190

申请日：1998-10-02

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C7/02

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

摘要翻译： 动态半导体存储器件由沿着多个位线对排列的多个动态存储器单元和与多个位线对相关联的多个动态读出放大器组成，每个读出放大器具有连接的一对MOS晶体管 到相应的一对位线。 在一个实施例中，读出放大器之一的第一和第二晶体管和与其相邻的另一个读出放大器的第一和第二晶体管位于由两个相邻的位线对限定的区域内。 每个位线对具有在与第二方向垂直的第一方向上延伸的第一和第二位线，其中源极和漏极区域形成在半导体衬底中，使得读出放大器的晶体管每四位排列一个 线在第二个方向。

公开(公告)号：US5864508A

公开(公告)日：1999-01-26

申请号：US879519

申请日：1997-06-20

申请人： Daisaburo Takashima ,  Yukihito Oowaki ,  Kenji Tsuchida ,  Masako Ohta

发明人： Daisaburo Takashima ,  Yukihito Oowaki ,  Kenji Tsuchida ,  Masako Ohta

IPC分类号： G11C11/407 ,  G11C11/408 ,  G11C7/04

CPC分类号： G11C11/4085 ,  G11C11/4087

摘要： A random-access memory includes an array of rows and columns of memory cells. Word lines are associated with rows of memory cells, bit lines lines are with columns of memory cells. A row decoder and a core control circuit are connected to the word lines. A column decoder and a sense amplifier circuit are connected to the bit lines. An individual cell may be addressed by addressing an individual column through a column decoder controlling the voltage on each word line, and through a row decoder controlling the voltage on each word line in response to specified row and column addresses input via row and column address buffers. A booster circuit provides the row decoder with a boosted voltage as a word-line drive voltage. This voltage has been transmitted to a pre-decoder section in the core control circuit before the row address is acquired in the row decoder.

摘要翻译： 随机存取存储器包括一列存储单元的行和列。 字线与存储单元行相关联，位线与存储单元列相关联。 行解码器和核心控制电路连接到字线。 列解码器和读出放大器电路连接到位线。 通过对控制每个字线上的电压的列解码器以及通过行解码器响应于经由行和列地址缓冲器输入的指定行和列地址来控制每个字线上的电压来寻址单个单元格 。 升压电路为行解码器提供升压电压作为字线驱动电压。 在行解码器中获取行地址之前，该电压被传送到核心控制电路中的预解码器部分。

公开(公告)号：US5222038A

公开(公告)日：1993-06-22

申请号：US782340

申请日：1991-10-24

申请人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

发明人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

IPC分类号： G11C11/4091 ,  G11C11/4094 ,  H01L27/108

CPC分类号： G11C11/4091 ,  G11C11/4094 ,  H01L27/10805

摘要： A dynamic random-access memory includes a plurality of spaced-apart memory cell blocks each of said memory cell blocks including rows and columns of memory cells arranged in a matrix on a substrate. Bit lines and word lines are connected to the rows and columns of memory cells in each cell block. PMOS sense amplifier sections and NMOS sense amplifier sections are associated with the memory cell blocks respectively. PMOS driver transistors for the PMOS sense amplifier sections are distributed among the PMOS sense amplifier sections such that a PMOS transistor is located between every two neighboring PMOS sense amplifier sections. NMOS driver transistors for the NMOS sense amplifier sections are distributed among the NMOS sense amplifier sections such that a NMOS transistor is located between every two neighboring NMOS sense amplifier sections. Source voltage supply lines extend in a corresponding word-line snap region between two neighboring cell blocks, and are connected to the PMOS and NMOS driver transistors, for supplying these transistors with a first and a second source voltage independently of each other.

摘要翻译： 动态随机存取存储器包括多个间隔开的存储单元块，每个所述存储单元块包括以矩阵形式布置在衬底上的行和列的存储单元。 位线和字线连接到每个单元块中的存储单元的行和列。 PMOS读出放大器部分和NMOS读出放大器部分分别与存储器单元块相关联。 用于PMOS读出放大器部分的PMOS驱动器晶体管分布在PMOS读出放大器部分之间，使得PMOS晶体管位于每两个相邻的PMOS读出放大器部分之间。 用于NMOS读出放大器部分的NMOS驱动器晶体管分布在NMOS读出放大器部分之间，使得NMOS晶体管位于每两个相邻的NMOS读出放大器部分之间。 源电压电源线在两个相邻单元块之间的相应字线捕捉区域中延伸，并且连接到PMOS和NMOS驱动晶体管，用于为彼此独立地提供第一和第二源电压的这些晶体管。

公开(公告)号：US5859805A

公开(公告)日：1999-01-12

申请号：US832818

申请日：1997-04-04

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

公开(公告)号：US5644525A

公开(公告)日：1997-07-01

申请号：US272284

申请日：1994-07-08

申请人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C7/06 ,  G11C11/4091 ,  H01L27/108 ,  G11C5/02 ,  G11C11/407 ,  G11C11/413

CPC分类号： G11C7/065 ,  G11C11/4091 ,  H01L27/108

摘要： A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connected to a corresponding pair of bit lines. In one embodiment, the first and second transistors of one of the sense amplifiers and the first and second transistors of another sense amplifier adjacent thereto are positioned within a region defined by two adjacent pairs of bit lines. Each of the bit line pairs has first and second bit lines extending in a first direction perpendicular to a second direction in which the source and drain regions are formed in the semiconductor substrate so that the transistors of the sense amplifiers are arranged one for every four bit lines in the second direction.

摘要翻译： 动态半导体存储器件由沿着多个位线对排列的多个动态存储器单元和与多个位线对相关联的多个动态读出放大器组成，每个读出放大器具有连接的一对MOS晶体管 到相应的一对位线。 在一个实施例中，读出放大器之一的第一和第二晶体管和与其相邻的另一个读出放大器的第一和第二晶体管位于由两个相邻的位线对限定的区域内。 每个位线对具有在与第二方向垂直的第一方向上延伸的第一和第二位线，其中源极和漏极区域形成在半导体衬底中，使得读出放大器的晶体管每四位排列一个 线在第二个方向。

公开(公告)号：US5144583A

公开(公告)日：1992-09-01

申请号：US461121

申请日：1990-01-04

申请人： Yukihito Oowaki ,  Kenji Tsuchida ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Kenji Tsuchida ,  Daisaburo Takashima

IPC分类号： G11C11/4097 ,  H01L23/528 ,  H01L27/108

CPC分类号： H01L27/10805 ,  G11C11/4097 ,  H01L23/528 ,  H01L2924/0002

摘要： A dynamic random-access memory has bit-line pairs, word lines intersecting with the bit-line pairs, and memory cells arranged at the intersections of the bit-line pairs and the word lines, and sense amplifiers provided for the bit-line pairs, respectively. One of every two neighboring bit-line pairs is twisted at one portion, thus forming a twisted crossing section. The twisted crossing section is made of the parts of the gate electrodes of the transistors incorporated in the sense amplifier connected to the twisted bit-line pair. The bit-line pairs is twisted at a portion substantially middle with respect to the direction in which it extends, and the sensr amplifier associated with this bit-line pair is located at the twisted portion thereof.

摘要翻译： 动态随机存取存储器具有位线对，与位线对相交的字线和布置在位线对和字线的交点处的存储单元，以及为位线对提供的读出放大器 ， 分别。 每两个相邻位线对中的一个在一部分被扭曲，从而形成扭曲的交叉部分。 扭转交叉部分由连接到扭绞位线对的读出放大器中的晶体管的栅电极的部分构成。 位线对在相对于其延伸的方向大致中间的部分处扭曲，并且与该位线对相关联的感应放大器位于其扭曲部分处。

公开(公告)号：US5084842A

公开(公告)日：1992-01-28

申请号：US536718

申请日：1990-06-12

申请人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

发明人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10805 ,  G11C11/4091 ,  G11C11/4094

摘要： A dynamic random access memory has a substrate, plural pairs of parallel bit lines provided on the substrate, parallel word lines insulatively crossing the parallel bit lines to define cross points therebetween, and memory cells provided at the cross points. Each memory cell has a data storage capacitor and a transistor. Sense amplifiers are provided at bit line pairs, respectively, to sense a data voltage. A discharge control section, which is associated with the sense amplifiers, forms discharge paths branched between the bit line pairs and the substrate grounded to progress the discharging of charges, when a certain word line is designated and a memory cell is selected from those memory cells which are connected to the certain word line, whereby the operational speed of the memory is increased.

摘要翻译： 动态随机存取存储器具有衬底，设置在衬底上的多对并行位线，并行字线绝对地穿过并行位线以限定它们之间的交叉点，以及设置在交叉点处的存储单元。 每个存储单元具有数据存储电容器和晶体管。 分别在位线对处提供感测放大器以感测数据电压。 与读出放大器相关联的放电控制部分在指定某个字线并且从那些存储器单元中选择存储器单元时，形成在位线对和衬底之间分支的放电路径，从而导致电荷的放电 其连接到某个字线，由此增加存储器的操作速度。

公开(公告)号：US5062077A

公开(公告)日：1991-10-29

申请号：US556470

申请日：1990-07-24

申请人： Daisaburo Takashima ,  Yukihito Oowaki ,  Kenji Tsuchida

发明人： Daisaburo Takashima ,  Yukihito Oowaki ,  Kenji Tsuchida

IPC分类号： G11C7/02 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/108

CPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/10805

摘要： A dynamic-type semiconductor memory device comprises bit lines, every two bit lines forming a folded bit line pair, every two pairs forming a bit-line unit such that one of the bit lines of the first pair extends between the bit lines of the second pair, and the bit lines of the second pair are twisted at middle portion, word lines intersecting with the bit lines, dummy word lines, extending parallel to the word lines, two of the dummy word lines being arranged on one side of the crossing portions of the bit lines of the second pair, and the other two of the dummy word lines being arranged on the other side of the crossing portions of the bit lines of the second pair, memory cells connected to selected ones of the intersections of the bit lines and the word lines, such that any adjacent memory cells connected to the same word line form a group which is arranged every two bit lines, and any adjacent two memory cells connected to the same bit line are shifted by half-pitch distance with respect to the corresponding two adjacent memory cells connected to either adjacent bit line, a plurality of dummy cells connected to selected ones of the intersections of the bit lines and the word lines, such that at least one dummy cell is connected to each bit line, and sense amplifiers provided for the pairs of bit lines, respectively.

摘要翻译： 动态型半导体存储器件包括位线，每两条位线形成折叠位线对，每两对形成位线单元，使得第一对的位线中的一条在第二对的位线之间延伸 并且第二对的位线在中间部分被扭曲，与位线相交的字线，与字线平行延伸的虚拟字线，两个虚拟字线被布置在交叉部分的一侧 并且另外两个虚拟字线被布置在第二对的位线的交叉部分的另一侧上，连接到位线的所选交叉点中的所选位置的存储器单元 和字线，使得连接到相同字线的任何相邻的存储单元形成每两位排布置的组，并且连接到同一位线的任何相邻的两个存储单元偏移半间距距离， 相对于连接到相邻位线的相应的两个相邻存储单元，连接到位线和字线的所选交叉的多个虚拟单元，使得至少一个虚设单元连接到每个位线， 以及分别为位线对提供的读出放大器。

公开(公告)号：US5933380A

公开(公告)日：1999-08-03

申请号：US871587

申请日：1997-06-09

申请人： Kenji Tsuchida ,  Yukihito Oowaki ,  Kazunori Ohuchi

发明人： Kenji Tsuchida ,  Yukihito Oowaki ,  Kazunori Ohuchi

IPC分类号： H01L21/8242 ,  G11C7/18 ,  G11C11/401 ,  H01L27/108 ,  G11C7/02

CPC分类号： G11C7/18

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells, the memory cell array being divided into a plurality of blocks, a plurality first bitlines arranged in each of the blocks, the plurality of first bitlines forming a plurality of first bitline pair each having a folded bitline structure with two of the plurality of first bitlines as a basic unit, a plurality second bitlines arranged to correspond to at least one of the blocks and formed above the first bitlines, the plurality of second bitlines forming a plurality of second bitline pair each having a folded bitline structure with two of the plurality of second bitlines as a basic unit, a plurality of sense amplifier circuits, arranged to correspond to the plurality of second bitline pairs, for detecting and amplifying information stored in the memory cells, and a plurality of select circuits for selecting one of two of first bitlines included in one of the plurality of first bitline pairs to selectively connect a selected first bitline with one of two of second bitlines included in one of the plurality of second bitline pairs.

摘要翻译： 半导体存储器件包括具有多个存储单元的存储单元阵列，该存储单元阵列被划分为多个块，多个第一位线布置在每个块中，多个第一位线形成多个第一位线 所述多个第二位线具有折叠的位线结构，其中所述多个第一位线中的两个作为基本单元，多个第二位线被布置成对应于所述块中的至少一个并且形成在所述第一位线上方，所述多个第二位线形成多个 第二位线对，其具有折叠的位线结构，其中所述多个第二位线中的两个作为基本单元;多个读出放大器电路，被布置为对应于所述多个第二位线对，用于检测和放大存储在所述存储器单元中的信息 以及多个选择电路，用于选择包括在所述多个第一位线对之一中的两个第一位线之一至s 选择性地将所选择的第一位线与包括在所述多个第二位线对之一中的第二位线之一中的一个位线连接。

公开(公告)号：US5062079A

公开(公告)日：1991-10-29

申请号：US412930

申请日：1989-09-26

申请人： Kenji Tsuchida ,  Yukihito Oowaki

发明人： Kenji Tsuchida ,  Yukihito Oowaki

IPC分类号： G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C11/4091

摘要： A MOS type random access memory disclosed has a plurality of pairs of sequentially aligned folded type bit lines each of which has a first bit line and a second bit line. Memory cells are arranged at points of intersection between a memory cell word line and the first bit lines. Dummy cells are arranged at points of intersection of a dummy cell word line and the second bit lines. Sense amplifier circuits are connected to the bit line pairs, respectively. In a data read mode of the memory, when a bit data is read from a certain memory cell which is connected to a first word line selected and a first bit line of a selected bit line pair, a second bit line onto which a data voltage is read from a dummy cell of the selected bit line pair is forcedly fixed to a precharge voltage produced by a precharge voltage generator in a presented time interval after the first word line is selected and before a certain sense amplifier circuit connected to the selected bit line pair gets activated, whereby interference noise may be eliminated which is introduced onto the selected bit line pair from a bit line pair adjacent to the selected bit line pair.

摘要翻译： 所公开的MOS型随机存取存储器具有多对顺序排列的折叠型位线，每个位线具有第一位线和第二位线。 存储单元布置在存储单元字线和第一位线之间的交点处。 虚拟单元被布置在虚拟单元字线和第二位线的交点处。 感测放大器电路分别连接到位线对。 在存储器的数据读取模式中，当从连接到所选位置的第一字线和选定位线对的第一位线的特定存储器单元读取位数据时，将数据电压 从所选择的位线对的虚拟单元中读取的数据被强制地固定在由预充电电压发生器产生的预充电电压之后，在选择第一字线之后的所呈现的时间间隔内，并且在连接到所选择的位线之前的某个读出放大器电路 对可以被激活，由此可以消除干扰噪声，其从与所选位线对相邻的位线对引入到所选位线对上。